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Added more generic _TECHMAP_ wire mechanism to techmap pass
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3 changed files with 193 additions and 79 deletions
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@ -204,6 +204,12 @@ struct RTLIL::Selection {
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bool selected_whole_module(RTLIL::IdString mod_name) const;
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bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
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void optimize(RTLIL::Design *design);
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template<typename T1> void select(T1 *module) {
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if (!full_selection && selected_modules.count(module->name) == 0) {
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selected_modules.insert(module->name);
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selected_members.erase(module->name);
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}
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}
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template<typename T1, typename T2> void select(T1 *module, T2 *member) {
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if (!full_selection && selected_modules.count(module->name) == 0)
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selected_members[module->name].insert(member->name);
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