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qlf_k6n10f: New ql_dsp pass, move to DSPV2

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This commit is contained in:
Martin Povišer 2025-02-04 10:30:15 +01:00
parent 8bb24badf2
commit 531374bec1
6 changed files with 1553 additions and 4409 deletions
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58
techlibs/quicklogic/ql_dsp.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
PRIVATE_NAMESPACE_BEGIN
USING_YOSYS_NAMESPACE
#include "ql_dsp_pm.h"
struct QlDspPass : Pass {
QlDspPass() : Pass("ql_dsp", "pack into QuickLogic DSPs") {}
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
log_header(d, "Executing QL_DSP pass. (pack into QuickLogic DSPs)\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
break;
}
extra_args(args, argidx, d);
for (auto module : d->selected_modules()) {
{
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_pack_regs();
}
{
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_cascade();
}
{
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_pack_regs();
}
}
}
} QlDspPass;
PRIVATE_NAMESPACE_END