mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-29 21:36:33 +00:00
Fixup sign.
This commit is contained in:
parent
ad912bc787
commit
52baeaef74
3 changed files with 26 additions and 6 deletions
|
|
@ -1876,10 +1876,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
||||
child->children[0] = AstNode::mkconst_str(loc, it->second.decode_string());
|
||||
else {
|
||||
bool is_signed = child->is_signed;
|
||||
if (!is_signed && !child->children.empty() && child->children[0] && child->children[0]->type == AST_CONSTANT)
|
||||
is_signed = child->children[0]->is_signed;
|
||||
is_signed = is_signed || ((it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
||||
bool is_signed = child->is_signed || ((it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
||||
child->children[0] = AstNode::mkconst_bits(loc, it->second.to_bits(), is_signed, (it->second.flags & RTLIL::CONST_FLAG_UNSIZED) != 0);
|
||||
}
|
||||
rewritten.insert(it->first);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue