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Added GP_DAC cell

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Andrew Zonenberg 2016-07-11 22:45:55 -07:00
parent baae472b83
commit 52a738a544
1 changed files with 8 additions and 0 deletions
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8
techlibs/greenpak4/cells_sim.v
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@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
endmodule endmodule
module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
initial VOUT = 0;
//analog hard IP is not supported for simulation
endmodule
module GP_DELAY(input IN, output reg OUT); module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1; parameter DELAY_STEPS = 1;