Merge pull request #5473 from YosysHQ/krys/unsized_params

Handle unsized params

tests/rtlil/everything.v

@@ -38,3 +38,20 @@ module foo(
     assign b = bb;
     assign y = a + bb;
 endmodule
+
+module set_param #(
+    parameter [3:0] VALUE = 1'bx
+) (
+    output logic [3:0] out
+);
+    assign out = VALUE;
+endmodule
+
+module use_param (
+    output logic [3:0] a, b, c, d
+);
+    set_param #($signed(1)) spa (a);
+    set_param #('1) spb (b);
+    set_param #(1.1) spc (c);
+    set_param #(1'b1) spd (d);
+endmodule

tests/verilog/unbased_unsized.sv

@@ -5,7 +5,20 @@ module pass_through(
     assign out = inp;
 endmodule
 
+module set_param #(
+    parameter logic [63:0] VALUE
+) (
+    output logic [63:0] out
+);
+    assign out = VALUE;
+endmodule
+
 module top;
+    localparam logic [63:0]
+        l01 = '0,
+        l02 = '1,
+        l03 = 'x,
+        l04 = 'z;
     logic [63:0]
         o01, o02, o03, o04,
         o05, o06, o07, o08,
@@ -23,6 +36,10 @@ module top;
     pass_through pt10('1, o10);
     pass_through pt11('x, o11);
     pass_through pt12('z, o12);
+    set_param #('0) sp13(o13);
+    set_param #('1) sp14(o14);
+    set_param #('x) sp15(o15);
+    set_param #('z) sp16(o16);
     always @* begin
         assert (o01 === {64 {1'b0}});
         assert (o02 === {64 {1'b1}});
@@ -36,5 +53,13 @@ module top;
         assert (o10 === {64 {1'b1}});
         assert (o11 === {64 {1'bx}});
         assert (o12 === {64 {1'bz}});
+        assert (l01 === {64 {1'b0}});
+        assert (l02 === {64 {1'b1}});
+        assert (l03 === {64 {1'bx}});
+        assert (l04 === {64 {1'bz}});
+        assert (o13 === {64 {1'b0}});
+        assert (o14 === {64 {1'b1}});
+        assert (o15 === {64 {1'bx}});
+        assert (o16 === {64 {1'bz}});
     end
 endmodule

tests/verilog/unbased_unsized.ys

@@ -1,5 +1,5 @@
 read_verilog -sv unbased_unsized.sv
-hierarchy
+hierarchy -top top
 proc
 flatten
 opt -full