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xilinx: Add simulation model for IBUFG.

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This commit is contained in:
Marcin Kościelnicki 2019-10-10 11:31:33 +02:00
parent 3fb604c75d
commit 526fe4cb89
5 changed files with 14 additions and 33 deletions
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10
techlibs/xilinx/xc7_cells_xtra.v
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@ -3932,16 +3932,6 @@ module IBUFDS_INTERMDISABLE (...);
input INTERMDISABLE;
endmodule
module IBUFG (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O;
(* iopad_external_pin *)
input I;
endmodule
module IBUFGDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";