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xilinx: Add simulation model for IBUFG.

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This commit is contained in:
Marcin Kościelnicki 2019-10-10 11:31:33 +02:00
parent 3fb604c75d
commit 526fe4cb89
5 changed files with 14 additions and 33 deletions
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11
techlibs/xilinx/cells_sim.v
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@ -38,6 +38,17 @@ module IBUF(
assign O = I;
endmodule
module IBUFG(
output O,
(* iopad_external_pin *)
input I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
assign O = I;
endmodule
module OBUF(
(* iopad_external_pin *)
output O,