mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-25 13:47:02 +00:00
Revert "Fix TODOs"
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
This commit is contained in:
parent
6d68972619
commit
52583ecff8
2 changed files with 20 additions and 0 deletions
|
@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
sigM = P;
|
sigM = P;
|
||||||
|
// TODO: Check if necessary
|
||||||
|
// This sigM could have no users if downstream $add
|
||||||
|
// is narrower than $mul result, for example
|
||||||
|
if (sigM.empty())
|
||||||
|
reject;
|
||||||
|
|
||||||
clock = port(dsp, \CLK, SigBit());
|
clock = port(dsp, \CLK, SigBit());
|
||||||
endcode
|
endcode
|
||||||
|
@ -154,6 +159,16 @@ match preAdd
|
||||||
optional
|
optional
|
||||||
endmatch
|
endmatch
|
||||||
|
|
||||||
|
code sigA sigD
|
||||||
|
// TODO: Check if this is necessary?
|
||||||
|
if (preAdd) {
|
||||||
|
sigA = port(preAdd, \A);
|
||||||
|
sigD = port(preAdd, \B);
|
||||||
|
if (GetSize(sigA) < GetSize(sigD))
|
||||||
|
std::swap(sigA, sigD);
|
||||||
|
}
|
||||||
|
endcode
|
||||||
|
|
||||||
// (4) If pre-adder was present, find match 'A' input for A2REG
|
// (4) If pre-adder was present, find match 'A' input for A2REG
|
||||||
// If pre-adder was not present, move ADREG to A2REG
|
// If pre-adder was not present, move ADREG to A2REG
|
||||||
// Then match 'A' input for A1REG
|
// Then match 'A' input for A1REG
|
||||||
|
|
|
@ -79,6 +79,11 @@ endcode
|
||||||
// (attached to at most two $mux cells that implement clock-enable or
|
// (attached to at most two $mux cells that implement clock-enable or
|
||||||
// reset functionality, using the in_dffe subpattern)
|
// reset functionality, using the in_dffe subpattern)
|
||||||
code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
|
code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
|
||||||
|
// TODO: Any downside to allowing this?
|
||||||
|
// If this DSP implements an accumulator, do not attempt to match
|
||||||
|
if (sigC == sigP)
|
||||||
|
reject;
|
||||||
|
|
||||||
argQ = sigC;
|
argQ = sigC;
|
||||||
subpattern(in_dffe);
|
subpattern(in_dffe);
|
||||||
if (dff) {
|
if (dff) {
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue