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https://github.com/YosysHQ/yosys
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Use more ID::{A,B,Y,blackbox,whitebox}
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parent
6cd8cace0c
commit
52355f5185
40 changed files with 889 additions and 887 deletions
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@ -89,7 +89,7 @@ struct ExtractFaWorker
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ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
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ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
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{
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SigBit y = sigmap(SigBit(cell->getPort(ID(Y))));
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SigBit y = sigmap(SigBit(cell->getPort(ID::Y)));
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log_assert(driver.count(y) == 0);
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driver[y] = cell;
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}
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@ -262,8 +262,8 @@ struct ExtractFaWorker
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pool<SigBit> new_leaves = leaves;
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new_leaves.erase(bit);
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if (cell->hasPort(ID(A))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(A)))));
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if (cell->hasPort(ID(B))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(B)))));
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if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A))));
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if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B))));
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if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C)))));
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if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D)))));
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@ -277,8 +277,8 @@ struct ExtractFaWorker
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void assign_new_driver(SigBit bit, SigBit new_driver)
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{
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Cell *cell = driver.at(bit);
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if (sigmap(cell->getPort(ID(Y))) == bit) {
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cell->setPort(ID(Y), module->addWire(NEW_ID));
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if (sigmap(cell->getPort(ID::Y)) == bit) {
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cell->setPort(ID::Y, module->addWire(NEW_ID));
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module->connect(bit, new_driver);
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}
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}
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@ -395,15 +395,15 @@ struct ExtractFaWorker
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log(" Created $fa cell %s.\n", log_id(cell));
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cell->setPort(ID(A), f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort(ID(B), f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
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X = module->addWire(NEW_ID);
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Y = module->addWire(NEW_ID);
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cell->setPort(ID(X), X);
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cell->setPort(ID(Y), Y);
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cell->setPort(ID::Y, Y);
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facache[fakey] = make_tuple(X, Y, cell);
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}
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@ -501,15 +501,15 @@ struct ExtractFaWorker
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log(" Created $fa cell %s.\n", log_id(cell));
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cell->setPort(ID(A), f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort(ID(B), f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort(ID(C), State::S0);
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X = module->addWire(NEW_ID);
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Y = module->addWire(NEW_ID);
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cell->setPort(ID(X), X);
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cell->setPort(ID(Y), Y);
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cell->setPort(ID::Y, Y);
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}
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if (func2.at(key).count(xor2_func)) {
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