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https://github.com/YosysHQ/yosys
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Use more ID::{A,B,Y,blackbox,whitebox}
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parent
6cd8cace0c
commit
52355f5185
40 changed files with 889 additions and 887 deletions
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@ -48,7 +48,7 @@ struct OptMergeWorker
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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SigSpec sig_s = conn.at(ID(S));
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SigSpec sig_b = conn.at(ID(B));
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SigSpec sig_b = conn.at(ID::B);
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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@ -60,11 +60,11 @@ struct OptMergeWorker
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std::sort(sb_pairs.begin(), sb_pairs.end());
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conn[ID(S)] = SigSpec();
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conn[ID(B)] = SigSpec();
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conn[ID::B] = SigSpec();
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for (auto &it : sb_pairs) {
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conn[ID(S)].append(it.first);
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conn[ID(B)].append(it.second);
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conn[ID::B].append(it.second);
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}
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}
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@ -97,28 +97,28 @@ struct OptMergeWorker
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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alt_conn = *conn;
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if (assign_map(alt_conn.at(ID(A))) < assign_map(alt_conn.at(ID(B)))) {
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alt_conn[ID(A)] = conn->at(ID(B));
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alt_conn[ID(B)] = conn->at(ID(A));
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if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) {
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alt_conn[ID::A] = conn->at(ID::B);
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alt_conn[ID::B] = conn->at(ID::A);
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}
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conn = &alt_conn;
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} else
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID(A)));
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alt_conn.at(ID(A)).sort();
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort();
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conn = &alt_conn;
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} else
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID(A)));
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alt_conn.at(ID(A)).sort_and_unify();
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort_and_unify();
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conn = &alt_conn;
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} else
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if (cell->type == ID($pmux)) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID(A)));
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assign_map.apply(alt_conn.at(ID(B)));
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assign_map.apply(alt_conn.at(ID::A));
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assign_map.apply(alt_conn.at(ID::B));
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assign_map.apply(alt_conn.at(ID(S)));
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sort_pmux_conn(alt_conn);
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conn = &alt_conn;
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@ -191,24 +191,24 @@ struct OptMergeWorker
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if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
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cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) {
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if (conn1.at(ID(A)) < conn1.at(ID(B))) {
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RTLIL::SigSpec tmp = conn1[ID(A)];
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conn1[ID(A)] = conn1[ID(B)];
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conn1[ID(B)] = tmp;
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if (conn1.at(ID::A) < conn1.at(ID::B)) {
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RTLIL::SigSpec tmp = conn1[ID::A];
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conn1[ID::A] = conn1[ID::B];
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conn1[ID::B] = tmp;
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}
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if (conn2.at(ID(A)) < conn2.at(ID(B))) {
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RTLIL::SigSpec tmp = conn2[ID(A)];
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conn2[ID(A)] = conn2[ID(B)];
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conn2[ID(B)] = tmp;
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if (conn2.at(ID::A) < conn2.at(ID::B)) {
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RTLIL::SigSpec tmp = conn2[ID::A];
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conn2[ID::A] = conn2[ID::B];
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conn2[ID::B] = tmp;
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}
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} else
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if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) {
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conn1[ID(A)].sort();
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conn2[ID(A)].sort();
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conn1[ID::A].sort();
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conn2[ID::A].sort();
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} else
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if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) {
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conn1[ID(A)].sort_and_unify();
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conn2[ID(A)].sort_and_unify();
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conn1[ID::A].sort_and_unify();
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conn2[ID::A].sort_and_unify();
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} else
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if (cell1->type == ID($pmux)) {
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sort_pmux_conn(conn1);
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