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Merge pull request #3909 from YosysHQ/widelut

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Default nowidelut for xo2/3/3d
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Miodrag Milanović 2023-08-29 11:04:49 +02:00 committed by GitHub
parent 572ad341b7 a42c630264
commit 51ddfb1f8e
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 18 additions and 6 deletions
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12
techlibs/lattice/synth_lattice.cc
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@ -102,6 +102,10 @@ struct SynthLatticePass : public ScriptPass
log("\n"); log("\n");
log(" -nowidelut\n"); log(" -nowidelut\n");
log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
log(" (by default enabled on MachXO2/XO3/XO3D)\n");
log("\n");
log(" -widelut\n");
log(" force use of PFU muxes to implement LUTs larger than LUT4s\n");
log("\n"); log("\n");
log(" -asyncprld\n"); log(" -asyncprld\n");
log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n"); log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
@ -163,6 +167,7 @@ struct SynthLatticePass : public ScriptPass
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
string run_from, run_to; string run_from, run_to;
bool force_widelut = false;
clear_flags(); clear_flags();
size_t argidx; size_t argidx;
@ -230,6 +235,12 @@ struct SynthLatticePass : public ScriptPass
} }
if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") { if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
nowidelut = true; nowidelut = true;
force_widelut = true;
continue;
}
if (args[argidx] == "-widelut") {
nowidelut = false;
force_widelut = true;
continue; continue;
} }
if (args[argidx] == "-abc2") { if (args[argidx] == "-abc2") {
@ -273,6 +284,7 @@ struct SynthLatticePass : public ScriptPass
arith_map = "_ccu2d"; arith_map = "_ccu2d";
brams_map = "_8kc"; brams_map = "_8kc";
have_dsp = false; have_dsp = false;
if (!force_widelut) nowidelut = true;
/* } else if (family == "xo" || /* } else if (family == "xo" ||
family == "pm") { family == "pm") {
} else if (family == "xp" || } else if (family == "xp" ||

2
tests/arch/machxo2/fsm.ys
View file

@ -3,7 +3,7 @@ hierarchy -top fsm
proc proc
flatten flatten
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
miter -equiv -make_assert -flatten gold gate miter miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

2
tests/arch/machxo2/lutram.ys
View file

@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r hierarchy -top lutram_1w1r
proc proc
memory -nomap memory -nomap
equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2
memory memory
opt -full opt -full

8
tests/arch/machxo2/mux.ys
View file

@ -3,7 +3,7 @@ design -save read
hierarchy -top mux2 hierarchy -top mux2
proc proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux4 hierarchy -top mux4
proc proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux8 hierarchy -top mux8
proc proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4 select -assert-count 5 t:LUT4
@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
design -load read design -load read
hierarchy -top mux16 hierarchy -top mux16
proc proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 -nowidelut # equivalency check equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4 select -assert-max 12 t:LUT4