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Merge pull request #4654 from YosysHQ/micko/vhdl_assert

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N. Engelhardt 2024-10-14 15:05:22 +02:00 committed by GitHub
parent 61ed9b6263 8d2b63bb8a
commit 518b6aec36
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1 changed files with 6 additions and 7 deletions
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13
frontends/verific/verific.cc
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@ -2142,13 +2142,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (verific_verbose) if (verific_verbose)
log(" assert condition %s.\n", log_signal(cond)); log(" assert condition %s.\n", log_signal(cond));
const char *assume_attr = nullptr; // inst->GetAttValue("assume"); Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
Cell *cell = nullptr; // used by rest of design logic, to prevent failing on
if (assume_attr != nullptr && !strcmp(assume_attr, "1")) // initial uninitialized state
cell = module->addAssume(new_verific_id(inst), cond, State::S1); if (cond.is_wire() && !cond.wire->name.isPublic())
else cond.wire->attributes[ID::init] = Const(1,1);
cell = module->addAssert(new_verific_id(inst), cond, State::S1);
import_attributes(cell->attributes, inst); import_attributes(cell->attributes, inst);
continue; continue;