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WIP aditional DFF primitives

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This commit is contained in:
Pepijn de Vos 2019-09-05 19:12:47 +02:00
parent 47374a495d
commit 5168b6ffa4
2 changed files with 48 additions and 1 deletions
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techlibs/gowin/cells_sim.v
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@ -62,6 +62,8 @@ module DFFR (output reg Q, input D, CLK, RESET);
end
endmodule // DFFR (positive clock edge; synchronous reset)
// TODO add more DFF sim cells
module VCC(output V);
assign V = 1;
endmodule