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	Add support for real-valued parameters + preserve type of parameters
This commit adds support for real-valued parameters in blackboxes. Additionally,
parameters now retain their types are no longer all encoded as strings.
There is a caveat with this implementation due to my limited knowledge of yosys,
more specifically to how yosys encodes bitwidths of parameter values. The example
below can motivate the implementation choice I took. Suppose a verilog component
is declared with the following parameters:
            parameter signed [26:0] test_signed;
            parameter        [26:0] test_unsigned;
            parameter signed [40:0] test_signed_large;
If you instantiate it as follows:
            defparam <inst_name> .test_signed = 49;
            defparam <inst_name> .test_unsigned = 40'd35;
            defparam <inst_name> .test_signed_large = 40'd12;
If you peek in the RTLIL::Const structure corresponding to these params, you
realize that parameter "test_signed" is being considered as a 32-bit value
since it's declared as "49" without a width specifier, even though the parameter
is defined to have a maximum width of 27 bits.
A similar issue occurs for parameter "test_unsigned" where it is supposed to take
a maximum bit width of 27 bits, but if the user supplies a 40-bit value as above,
then yosys considers the value to be 40 bits.
I suppose this is due to the type being defined by the RHS rather than the definition.
Regardless of this, I emit the same widths as what the user specifies on the RHS when
generating firrtl IR.
			
			
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					 1 changed files with 115 additions and 40 deletions
				
			
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			@ -102,56 +102,128 @@ const char *make_id(IdString id)
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	return namecache.at(id).c_str();
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}
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std::string dump_const_string(const RTLIL::Const &data)
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{
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	std::string res_str;
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	std::string str = data.decode_string();
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	for (size_t i = 0; i < str.size(); i++)
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	{
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		if (str[i] == '\n')
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			res_str += "\\n";
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		else if (str[i] == '\t')
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			res_str += "\\t";
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		else if (str[i] < 32)
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			res_str += stringf("\\%03o", str[i]);
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		else if (str[i] == '"')
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			res_str += "\\\"";
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		else if (str[i] == '\\')
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			res_str += "\\\\";
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		else
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			res_str += str[i];
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	}
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	return res_str;
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}
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std::string dump_const(const RTLIL::Const &data)
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{
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	std::string dataStr;
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	std::string res_str;
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	dataStr += "\"";
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	// // For debugging purposes to find out how Yosys encodes flags.
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	// res_str += stringf("flags_%x --> ", data.flags);
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	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0)
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	// Real-valued parameter.
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	if (data.flags & RTLIL::CONST_FLAG_REAL)
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	{
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		// Emit binary prefix for string.
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		dataStr += "b";
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		// Emit bits.
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		int width = data.bits.size();
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		for (int i = width - 1; i >= 0; i--)
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		{
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			log_assert(i < width);
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			switch (data.bits[i])
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			{
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				case State::S0: dataStr += stringf("0"); break;
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				case State::S1: dataStr += stringf("1"); break;
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				case State::Sx: dataStr += stringf("x"); break;
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				case State::Sz: dataStr += stringf("z"); break;
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				case State::Sa: dataStr += stringf("-"); break;
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				case State::Sm: dataStr += stringf("m"); break;
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			}
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		}
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		// Yosys stores real values as strings, so we call the string dumping code.
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		res_str += dump_const_string(data);
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	}
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	// String parameter.
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	else if (data.flags & RTLIL::CONST_FLAG_STRING)
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	{
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		res_str += "\"";
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		res_str += dump_const_string(data);
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		res_str += "\"";
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	}
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	// Numeric (non-real) parameter.
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	else
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	{
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		std::string str = data.decode_string();
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		for (size_t i = 0; i < str.size(); i++)
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		int width = data.bits.size();
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		// If a standard 32-bit int, then emit standard int value like "56" or
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		// "-56". Firrtl supports negative-valued int literals.
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		//
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		//    SignedInt
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		//      : ( '+' | '-' ) PosInt
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		//      ;
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		if (width <= 32)
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		{
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			if (str[i] == '\n')
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				dataStr += "\\n";
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			else if (str[i] == '\t')
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				dataStr += "\\t";
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			else if (str[i] < 32)
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				dataStr += stringf("\\%03o", str[i]);
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			else if (str[i] == '"')
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				dataStr += "\\\"";
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			else if (str[i] == '\\')
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				dataStr += "\\\\";
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			else
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				dataStr += str[i];
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			int32_t int_val = 0;
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			for (int i = 0; i < width; i++)
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			{
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				switch (data.bits[i])
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				{
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					case State::S0:                      break;
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					case State::S1: int_val |= (1 << i); break;
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					default:
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						log_error("Unexpected int value\n");
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						break;
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				}
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			}
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			res_str += stringf("%d", int_val);
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		}
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		else
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		{
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			// If value is larger than 32 bits, then emit a binary representation of
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			// the number. We have to do this as firrtl number literals don't support
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			// specifying their width, therefore a binary literal is the only way to
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			// guarantee the parameter widths match that provided on the RHS of a
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			// verilog parameter assignment. There is a caveat to this approach
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			// though:
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			//
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			// Note that parameter may be defined as having a fixed width as follows:
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			//
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			//     parameter signed [26:0] test_signed;
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			//     parameter        [26:0] test_unsigned;
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			//     parameter signed [40:0] test_signed_large;
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			//
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			// However, if you assign a value on the RHS without specifying the
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			// precision, then yosys considers the value you used as an int and
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			// assigns it a width of 32 bits regardless of the type of the parameter.
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			//
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			// 		defparam <inst_name> .test_signed = 49;						(width = 32, though should be 27 based on definition)
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			// 		defparam <inst_name> .test_unsigned = 40'd35;			(width = 40, though should be 27 based on definition)
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			// 		defparam <inst_name> .test_signed_large = 40'd12;	(width = 40)
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			//
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			// We therefore may lose the precision of the original verilog literal if
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			// it was written without it's bitwidth specifier.
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			// Emit binary prefix for string.
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			res_str += "\"b";
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			// Emit bits.
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			for (int i = width - 1; i >= 0; i--)
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			{
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				log_assert(i < width);
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				switch (data.bits[i])
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				{
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					case State::S0: res_str += "0"; break;
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					case State::S1: res_str += "1"; break;
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					case State::Sx: res_str += "x"; break;
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					case State::Sz: res_str += "z"; break;
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					case State::Sa: res_str += "-"; break;
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					case State::Sm: res_str += "m"; break;
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				}
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			}
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			res_str += "\"";
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		}
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	}
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	dataStr += "\"";
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	return dataStr;
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	return res_str;
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}
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std::string extmodule_name(RTLIL::Cell *cell, RTLIL::Module *mod_instance)
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			@ -216,8 +288,11 @@ void emit_extmodule(RTLIL::Cell *cell, RTLIL::Module *mod_instance, std::ostream
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	// Emit extmodule generic parameters.
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	for (const auto &p : cell->parameters)
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	{
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		std::string param_name(p.first.c_str());
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		const std::string param_value = dump_const(p.second);
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		const RTLIL::IdString p_id = p.first;
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		const RTLIL::Const p_value = p.second;
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		std::string param_name(p_id.c_str());
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		const std::string param_value = dump_const(p_value);
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		// Remove backslashes from parameters as these come from the internal RTLIL
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		// naming scheme, but should not exist in the emitted firrtl blackboxes.
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