Renamed some of the test cases in tests/simple to avoid name collisions

tests/simple/arraycells.v

@@ -1,5 +1,5 @@
 
-module test001(a, b, c, y);
+module array_test001(a, b, c, y);
 	input a;
 	input [31:0] b, c;
 	input [31:0] y;

tests/simple/fsm.v

@@ -1,7 +1,7 @@
 
 // `define ASYNC_RESET
 
-module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
+module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
 
 input clk, reset, button_a, button_b;
 output reg red_a, green_a, red_b, green_b;

tests/simple/generate.v

@@ -1,5 +1,5 @@
 
-module test1(clk, a, b, y);
+module gen_test1(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -40,7 +40,7 @@ endmodule
 
 // ------------------------------------------
 
-module test2(clk, a, b, y);
+module gen_test2(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -67,7 +67,7 @@ endmodule
 
 // ------------------------------------------
 
-module test3(a, b, sel, y, z);
+module gen_test3(a, b, sel, y, z);
 
 input [3:0] a, b;
 input sel;

tests/simple/i2c_master_tests.v

@@ -3,7 +3,7 @@
 // this core that triggered bugs in early versions of yosys.
 
 // from i2c_master_bit_ctrl
-module test01(clk, rst, nReset, al);
+module i2c_test01(clk, rst, nReset, al);
 
 	input clk, rst, nReset;
 	output reg al;
@@ -26,7 +26,7 @@ module test01(clk, rst, nReset, al);
 endmodule
 
 // from i2c_master_bit_ctrl
-module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
+module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
 
 	input clk, slave_wait, clk_cnt;
 	input cmd;

tests/simple/macros.v

@@ -237,7 +237,7 @@ end
 endmodule
 
 `define SIZE 4 // comment supported in this part
-module test ( din_a, dout_a );
+module test_comment_in_macro ( din_a, dout_a );
 input [`SIZE-1:0] din_a;
 output [`SIZE-1:0] dout_a;
 assign dout_a = din_a | `SIZE'ha;

tests/simple/mem2reg.v

@@ -1,5 +1,5 @@
 
-module test1(in_addr, in_data, out_addr, out_data);
+module mem2reg_test1(in_addr, in_data, out_addr, out_data);
 
 input [1:0] in_addr, out_addr;
 input [3:0] in_data;
@@ -19,7 +19,7 @@ endmodule
 
 // ------------------------------------------------------
 
-module test2(clk, mode, addr, data);
+module mem2reg_test2(clk, mode, addr, data);
 
 input clk, mode;
 input [2:0] addr;
@@ -46,7 +46,7 @@ endmodule
 // ------------------------------------------------------
 
 // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
-module test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
+module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
 reg [7:0] dint_c [0:7]; 
 always @(posedge clk)
   begin

tests/simple/memory.v

@@ -1,5 +1,5 @@
 
-module test00(clk, setA, setB, y);
+module memtest00(clk, setA, setB, y);
 
 input clk, setA, setB;
 output y;
@@ -16,7 +16,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
+module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
 
 input clk, wr_en;
 input [3:0] wr_addr, rd_addr;
@@ -36,7 +36,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
+module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
 
 input clk, setA, setB;
 input [1:0] addr;
@@ -77,7 +77,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -95,7 +95,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -116,7 +116,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test05(clk, addr, wdata, rdata, wen);
+module memtest05(clk, addr, wdata, rdata, wen);
 
 input clk;
 input [1:0] addr;
@@ -137,7 +137,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
     (* gentb_constant=0 *) wire rst;
     reg [7:0] test [0:7];
     integer i;
@@ -156,7 +156,7 @@ module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, outpu
     assign dout = test[idx];
 endmodule
 
-module test06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
     (* gentb_constant=0 *) wire rst;
     reg [7:0] test [0:7];
     integer i;
@@ -177,7 +177,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test07(clk, addr, woffset, wdata, rdata);
+module memtest07(clk, addr, woffset, wdata, rdata);
 
 input clk;
 input [1:0] addr;

tests/simple/operators.v

@@ -1,4 +1,4 @@
-module test(clk, mode, u1, s1, u2, s2, y);
+module optest(clk, mode, u1, s1, u2, s2, y);
 
 input clk;
 input [6:0] mode;

tests/simple/paramods.v

@@ -1,5 +1,5 @@
 
-module test1(a, b, x, y);
+module pm_test1(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -11,7 +11,7 @@ endmodule
 
 // -----------------------------------
 
-module test2(a, b, x, y);
+module pm_test2(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -23,7 +23,7 @@ endmodule
 
 // -----------------------------------
 
-module test3(a, b, x, y);
+module pm_test3(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;

tests/simple/partsel.v

@@ -1,4 +1,4 @@
-module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
+module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
 wire [5:0] offset = idx << 2;
 assign slice_up = data[offset +: 4];
 assign slice_down = data[offset + 3 -: 4];

tests/simple/repwhile.v

@@ -1,4 +1,4 @@
-module test001(input [5:0] a, output [7:0] y, output [31:0] x);
+module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x);
 
 	function [7:0] mylog2;
 		input [31:0] value;

tests/simple/signedexpr.v

@@ -1,4 +1,4 @@
-module test01(a, b, xu, xs, yu, ys, zu, zs);
+module signed_test01(a, b, xu, xs, yu, ys, zu, zs);
 
 input signed [1:0] a;
 input signed [2:0] b;

tests/simple/task_func.v

@@ -1,5 +1,5 @@
 
-module test01(clk, a, b, c, x, y, z, w);
+module task_func_test01(clk, a, b, c, x, y, z, w);
 
 input clk;
 input [7:0] a, b, c;

tests/simple/undef_eqx_nex.v

@@ -1,4 +1,4 @@
-module test(y);
+module undef_eqx_nex(y);
 output [7:0] y;
 assign y[0] = 0/0;
 assign y[1] = 0/1;

tests/simple/usb_phy_tests.v

@@ -1,6 +1,6 @@
 
 // from usb_rx_phy
-module test01(clk, rst, rx_en, fs_ce);
+module usb_phy_test01(clk, rst, rx_en, fs_ce);
 
 input		clk, rst;
 input		rx_en;