mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-07 03:31:24 +00:00
Code Activity

Renamed some of the test cases in tests/simple to avoid name collisions

Browse source
This commit is contained in:
Clifford Wolf 2014-07-25 13:01:45 +02:00
parent 0520bfea89
commit 50f22ff30c
15 changed files with 30 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

36
tests/simple/usb_phy_tests.v Normal file
View file

@ -0,0 +1,36 @@
// from usb_rx_phy
module usb_phy_test01(clk, rst, rx_en, fs_ce);
input clk, rst;
input rx_en;
output reg fs_ce;
reg [1:0] dpll_next_state;
reg [1:0] dpll_state;
always @(posedge clk)
dpll_state <= rst ? 0 : dpll_next_state;
always @*
begin
fs_ce = 1'b0;
case(dpll_state)
2'h0:
if(rx_en) dpll_next_state = 2'h0;
else dpll_next_state = 2'h1;
2'h1:begin
fs_ce = 1'b1;
if(rx_en) dpll_next_state = 2'h3;
else dpll_next_state = 2'h2;
end
2'h2:
if(rx_en) dpll_next_state = 2'h0;
else dpll_next_state = 2'h3;
2'h3:
if(rx_en) dpll_next_state = 2'h0;
else dpll_next_state = 2'h0;
endcase
end
endmodule