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Renamed some of the test cases in tests/simple to avoid name collisions
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15 changed files with 30 additions and 30 deletions
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@ -3,7 +3,7 @@
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// this core that triggered bugs in early versions of yosys.
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// from i2c_master_bit_ctrl
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module test01(clk, rst, nReset, al);
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module i2c_test01(clk, rst, nReset, al);
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input clk, rst, nReset;
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output reg al;
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@ -26,7 +26,7 @@ module test01(clk, rst, nReset, al);
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endmodule
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// from i2c_master_bit_ctrl
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module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
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module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
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input clk, slave_wait, clk_cnt;
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input cmd;
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