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Fix RAM64M model to have 6 bit address bus

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This commit is contained in:
Eddie Hung 2019-12-12 18:52:03 -08:00
parent 037d1a03df
commit 50e0c83560
1 changed files with 4 additions and 4 deletions
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8
techlibs/xilinx/cells_sim.v
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@ -1185,10 +1185,10 @@ module RAM64M (
output DOB,
output DOC,
output DOD,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,