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dff2ff: remove invalid test

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This commit is contained in:
Emil J. Tywoniak 2026-02-03 21:33:44 +01:00
parent 1561834bae
commit 50db1f428d
1 changed files with 0 additions and 16 deletions
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16
tests/techmap/dff2ff.ys
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@ -1,16 +0,0 @@
read_verilog -icells << EOT
module top(...);
input [1:0] D;
input C;
output [1:0] Q;
always @(posedge C)
Q <= D;
endmodule
EOT
proc
equiv_opt -assert techmap -map +/dff2ff.v