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Clean whitespace and permissions in techlibs/intel

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This commit is contained in:
Larry Doolittle 2017-10-04 17:01:30 -07:00 committed by Clifford Wolf
parent fc3378916d
commit 50bcd9a728
21 changed files with 190 additions and 190 deletions
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0
techlibs/intel/Makefile.inc Executable file → Normal file
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techlibs/intel/a10gx/cells_arith.v Executable file → Normal file
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techlibs/intel/a10gx/cells_map.v Executable file → Normal file
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@ -31,7 +31,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

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techlibs/intel/a10gx/cells_sim.v Executable file → Normal file
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techlibs/intel/common/brams.txt Executable file → Normal file
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techlibs/intel/common/brams_map.v Executable file → Normal file
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techlibs/intel/common/m9k_bb.v Executable file → Normal file
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techlibs/intel/cycloneiv/cells_arith.v Executable file → Normal file
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techlibs/intel/cycloneiv/cells_map.v Executable file → Normal file
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@ -62,7 +62,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

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techlibs/intel/cycloneiv/cells_sim.v Executable file → Normal file
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techlibs/intel/cycloneive/arith_map.v Executable file → Normal file
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techlibs/intel/cycloneive/cells_map.v Executable file → Normal file
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@ -61,7 +61,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

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techlibs/intel/cycloneive/cells_sim.v Executable file → Normal file
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techlibs/intel/cyclonev/cells_arith.v Executable file → Normal file
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techlibs/intel/cyclonev/cells_map.v Executable file → Normal file
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@ -60,7 +60,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

0
techlibs/intel/cyclonev/cells_sim.v Executable file → Normal file
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techlibs/intel/max10/cells_arith.v Executable file → Normal file
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techlibs/intel/max10/cells_map.v Executable file → Normal file
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@ -62,7 +62,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

0
techlibs/intel/max10/cells_sim.v Executable file → Normal file
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techlibs/intel/synth_intel.cc Executable file → Normal file
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