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Clean whitespace and permissions in techlibs/intel
This commit is contained in:
Larry Doolittle
Clifford Wolf
parent
fc3378916d
commit
50bcd9a728
21 changed files with 190 additions and 190 deletions
8
techlibs/intel/cyclonev/cells_arith.v
Executable file → Normal file
8
techlibs/intel/cyclonev/cells_arith.v
Executable file → Normal file
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@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
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//wire [Y_WIDTH:0] C = {CO, CI};
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wire [Y_WIDTH+1:0] COx;
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wire [Y_WIDTH+1:0] C = {COx, CI};
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/* Start implementation */
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(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
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if(i==Y_WIDTH-1) begin
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@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
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endgenerate
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/* End implementation */
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assign X = AA ^ BB;
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endmodule
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endmodule
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110
techlibs/intel/cyclonev/cells_map.v
Executable file → Normal file
110
techlibs/intel/cyclonev/cells_map.v
Executable file → Normal file
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@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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parameter WYSIWYG="TRUE";
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wire E_i = ~ E;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
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@ -60,89 +60,89 @@ module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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output Y;
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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end
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end
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else
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if (WIDTH == 2) begin
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cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(1'b1),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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end
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end
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else
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if(WIDTH == 3) begin
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cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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end
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end
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else
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if(WIDTH == 4) begin
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cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(1'b1),
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.dataf(1'b1),
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.datad(A[3]),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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end
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end
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else
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if(WIDTH == 5) begin
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if(WIDTH == 5) begin
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cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(1'b1),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(1'b1),
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.datag(1'b1));
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end
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end
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else
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if(WIDTH == 6) begin
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cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datag(1'b1));
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end
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end
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else
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if(WIDTH == 7) begin
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cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datag(A[6]));
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end
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end
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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20
techlibs/intel/cyclonev/cells_sim.v
Executable file → Normal file
20
techlibs/intel/cyclonev/cells_sim.v
Executable file → Normal file
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@ -25,23 +25,23 @@ module GND (output G);
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endmodule // GND
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/* Altera Cyclone V devices Input Buffer Primitive */
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module cyclonev_io_ibuf
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module cyclonev_io_ibuf
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(output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // cyclonev_io_ibuf
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/* Altera Cyclone V devices Output Buffer Primitive */
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module cyclonev_io_obuf
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module cyclonev_io_obuf
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(output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // cyclonev_io_obuf
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/* Altera Cyclone V LUT Primitive */
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module cyclonev_lcell_comb
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module cyclonev_lcell_comb
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(output combout, cout, sumout, shareout,
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input dataa, datab, datac, datad,
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input dataa, datab, datac, datad,
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input datae, dataf, datag, cin,
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input sharein);
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@ -59,8 +59,8 @@ module cyclonev_lcell_comb
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// Extended mode uses mux to define the output
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wire mux_0, mux_1;
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// Input for hold the shared LUT mode value
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wire shared_lut_alm;
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wire shared_lut_alm;
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// Simulation model of 4-input LUT
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function lut4;
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input [15:0] mask;
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@ -75,7 +75,7 @@ module cyclonev_lcell_comb
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lut4 = dataa ? s1[1] : s1[0];
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end
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endfunction // lut4
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// Simulation model of 5-input LUT
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function lut5;
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input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
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@ -119,7 +119,7 @@ endmodule // cyclonev_lcell_comb
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/* Altera D Flip-Flop Primitive */
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module dffeas
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module dffeas
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(output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload);
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@ -131,7 +131,7 @@ module dffeas
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reg q_tmp;
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wire reset;
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reg [7:0] debug_net;
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assign reset = (prn && sclr && ~clrn && ena);
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assign q = q_tmp & 1'b1;
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@ -140,5 +140,5 @@ module dffeas
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else q_tmp <= d;
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end
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assign q = q_tmp;
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endmodule // dffeas
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