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Clean whitespace and permissions in techlibs/intel
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fc3378916d
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21 changed files with 190 additions and 190 deletions
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@ -19,7 +19,7 @@
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/* No clearbox model */
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`ifdef NO_CLEARBOX
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(* blackbox *)
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module altpll
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module altpll
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( inclk,
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fbin,
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pllena,
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@ -62,7 +62,7 @@ module altpll
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c2,
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c3,
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c4);
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parameter intended_device_family = "MAX 10";
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parameter operation_mode = "NORMAL";
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parameter pll_type = "AUTO";
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@ -340,7 +340,7 @@ module altpll
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input phasestep;
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input configupdate;
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inout fbmimicbidir;
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output [width_clock-1:0] clk;
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output [3:0] extclk;
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@ -361,6 +361,6 @@ module altpll
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output fref;
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output icdrclk;
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output c0, c1, c2, c3, c4;
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endmodule // altpll
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`endif
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0
techlibs/intel/common/brams.txt
Executable file → Normal file
0
techlibs/intel/common/brams.txt
Executable file → Normal file
58
techlibs/intel/common/brams_map.v
Executable file → Normal file
58
techlibs/intel/common/brams_map.v
Executable file → Normal file
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@ -2,11 +2,11 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 36;
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parameter ABITS = "1";
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parameter DBITS = "1";
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parameter ABITS = "1";
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parameter DBITS = "1";
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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//Read data
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@ -19,7 +19,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
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input B1EN;
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wire [CFG_DBITS-1:0] B1DATA_t;
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localparam MODE = CFG_DBITS == 1 ? 1:
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CFG_DBITS == 2 ? 2:
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CFG_DBITS == 4 ? 3:
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@ -30,7 +30,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
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CFG_DBITS == 32 ? 8:
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CFG_DBITS == 36 ? 9:
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'bx;
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localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
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CFG_DBITS == 2 ? 4096:
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CFG_DBITS == 4 ? 2048:
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@ -41,32 +41,32 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
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CFG_DBITS == 32 ? 256:
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CFG_DBITS == 36 ? 256:
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'bx;
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altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
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.clock_enable_input_a ("ALTERNATE" ),
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.clock_enable_output_b ("NORMAL" ),
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.clock_enable_output_a ("NORMAL" ),
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.wrcontrol_aclr_a ("NONE" ),
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.indata_aclr_a ("NONE" ),
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.address_aclr_a ("NONE" ),
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.outdata_aclr_a ("NONE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.operation_mode ("SINGLE_PORT" ),
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.intended_device_family ("CYCLONE IVE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.lpm_type ("altsyncram" ),
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.init_type ("unused" ),
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altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
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.clock_enable_input_a ("ALTERNATE" ),
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.clock_enable_output_b ("NORMAL" ),
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.clock_enable_output_a ("NORMAL" ),
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.wrcontrol_aclr_a ("NONE" ),
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.indata_aclr_a ("NONE" ),
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.address_aclr_a ("NONE" ),
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.outdata_aclr_a ("NONE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.operation_mode ("SINGLE_PORT" ),
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.intended_device_family ("CYCLONE IVE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.lpm_type ("altsyncram" ),
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.init_type ("unused" ),
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.ram_block_type ("AUTO" ),
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.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
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.power_up_uninitialized ("FALSE"),
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.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
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.width_byteena_a (1), // Forced value
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.numwords_b ( NUMWORDS ),
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.numwords_a ( NUMWORDS ),
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.widthad_b ( CFG_ABITS ),
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.width_b ( CFG_DBITS ),
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.widthad_a ( CFG_ABITS ),
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.width_a ( CFG_DBITS )
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.numwords_b ( NUMWORDS ),
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.numwords_a ( NUMWORDS ),
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.widthad_b ( CFG_ABITS ),
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.width_b ( CFG_DBITS ),
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.widthad_a ( CFG_ABITS ),
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.width_a ( CFG_DBITS )
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) _TECHMAP_REPLACE_ (
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.data_a(B1DATA),
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.address_a(B1ADDR),
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@ -78,16 +78,16 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
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.wren_b(1'b0),
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.rden_b(1'b0),
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.q_b(1'b0),
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.clock0(CLK2),
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.clock0(CLK2),
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.clock1(1'b1), // Unused in single port mode
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.clocken0(1'b1),
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.clocken1(1'b1),
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.clocken2(1'b1),
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.clocken3(1'b1),
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.aclr0(1'b0),
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.aclr0(1'b0),
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.aclr1(1'b0),
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.addressstall_a(1'b0),
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.addressstall_b(1'b0));
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endmodule
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12
techlibs/intel/common/m9k_bb.v
Executable file → Normal file
12
techlibs/intel/common/m9k_bb.v
Executable file → Normal file
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@ -17,10 +17,10 @@
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*
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*/
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(* blackbox *)
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module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
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q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
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module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
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q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
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addressstall_a, addressstall_b);
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parameter clock_enable_input_b = "ALTERNATE";
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parameter clock_enable_input_a = "ALTERNATE";
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parameter clock_enable_output_b = "NORMAL";
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@ -33,7 +33,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
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parameter operation_mode = "SINGLE_PORT";
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parameter intended_device_family = "MAX 10 FPGA";
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parameter outdata_reg_a = "UNREGISTERED";
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parameter lpm_type = "altsyncram";
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parameter lpm_type = "altsyncram";
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parameter init_type = "unused";
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parameter ram_block_type = "AUTO";
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parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
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@ -46,7 +46,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
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parameter width_b = 1;
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parameter widthad_a = 1;
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parameter width_a = 1;
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// Port A declarations
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output [35:0] q_a;
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input [35:0] data_a;
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@ -66,5 +66,5 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
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input addressstall_a;
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input addressstall_b;
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// TODO: Implement the correct simulation model
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endmodule // altsyncram
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