mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 18:45:34 +00:00
Code Activity

Clean whitespace and permissions in techlibs/intel

Browse source
This commit is contained in:
Larry Doolittle 2017-10-04 17:01:30 -07:00 • committed by Clifford Wolf
parent fc3378916d
commit 50bcd9a728
21 changed files with 190 additions and 190 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/intel/a10gx/cells_arith.v Executable file → Normal file
View file

@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
endmodule

4
techlibs/intel/a10gx/cells_map.v Executable file → Normal file
View file

@ -31,13 +31,13 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin

2
techlibs/intel/a10gx/cells_sim.v Executable file → Normal file
View file

@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf
/* Altera Arria 10 GX LUT Primitive */
module twentynm_lcell_comb (output combout, cout, sumout,
input dataa, datab, datac, datad,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);