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Fixes in $alu SAT- and eval-models

This commit is contained in:
Clifford Wolf 2014-09-03 13:39:46 +02:00
parent 635b922afe
commit 50ac284823
2 changed files with 5 additions and 6 deletions

View file

@ -178,8 +178,8 @@ struct ConstEval
RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend(SIZE(sig_y), signed_a);
sig_b.extend(SIZE(sig_y), signed_b);
sig_a.extend_u0(SIZE(sig_y), signed_a);
sig_b.extend_u0(SIZE(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;