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Merge pull request #4899 from YosysHQ/shr_int_max

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Fix runtime error on shift by INT_MAX
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KrystalDelusion 2025-02-15 09:52:33 +13:00 committed by GitHub
parent df3c62a4ed 4c728968a3
commit 508e7327e4
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2 changed files with 13 additions and 0 deletions
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4
passes/opt/opt_expr.cc
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@ -1315,6 +1315,10 @@ skip_fine_alu:
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int()); RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
// and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX
shift_bits = min(shift_bits, GetSize(sig_a));
if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y)) if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());

9
tests/opt/opt_expr_shr_int_max.ys Normal file
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@ -0,0 +1,9 @@
read_verilog << EOF
module uut_00034(b, y);
input signed [30:0] b;
output [11:0] y = b >> ~31'b0; // shift by INT_MAX
endmodule
EOF
# This should succeed, even with UBSAN halt_on_error
opt_expr