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Merge pull request #4899 from YosysHQ/shr_int_max
Fix runtime error on shift by INT_MAX
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commit
508e7327e4
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@ -1315,6 +1315,10 @@ skip_fine_alu:
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
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// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
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// and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX
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shift_bits = min(shift_bits, GetSize(sig_a));
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if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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9
tests/opt/opt_expr_shr_int_max.ys
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9
tests/opt/opt_expr_shr_int_max.ys
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@ -0,0 +1,9 @@
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read_verilog << EOF
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module uut_00034(b, y);
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input signed [30:0] b;
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output [11:0] y = b >> ~31'b0; // shift by INT_MAX
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endmodule
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EOF
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# This should succeed, even with UBSAN halt_on_error
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opt_expr
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