mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length
This commit is contained in:
Eddie Hung
parent
5445cd4d00
commit
505e4c2d59
2 changed files with 84 additions and 108 deletions
|
|
@ -176,19 +176,30 @@ struct ShregmapTechXilinx7 : ShregmapTech
|
|||
{
|
||||
const auto &tap = *taps.begin();
|
||||
auto bit = tap.second;
|
||||
|
||||
auto it = sigbit_to_shiftx_offset.find(bit);
|
||||
// If fixed-length, no fixup necessary
|
||||
if (it == sigbit_to_shiftx_offset.end())
|
||||
return true;
|
||||
|
||||
auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
|
||||
newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
|
||||
newcell->setParam("\\INIT", cell->getParam("\\INIT"));
|
||||
newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
|
||||
newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
|
||||
|
||||
newcell->setPort("\\C", cell->getPort("\\C"));
|
||||
newcell->setPort("\\D", cell->getPort("\\D"));
|
||||
newcell->setPort("\\E", cell->getPort("\\E"));
|
||||
|
||||
Cell* shiftx = it->second.first;
|
||||
|
||||
cell->setPort("\\L", shiftx->getPort("\\B"));
|
||||
cell->setPort("\\Q", shiftx->getPort("\\Y"));
|
||||
newcell->setPort("\\L", shiftx->getPort("\\B"));
|
||||
newcell->setPort("\\Q", shiftx->getPort("\\Y"));
|
||||
|
||||
cell->module->remove(shiftx);
|
||||
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -442,8 +453,6 @@ start_cell:
|
|||
|
||||
first_cell->type = shreg_cell_type_str;
|
||||
first_cell->setPort(q_port, last_cell->getPort(q_port));
|
||||
if (!first_cell->hasPort("\\L"))
|
||||
first_cell->setPort("\\L", depth-1);
|
||||
first_cell->setParam("\\DEPTH", depth);
|
||||
|
||||
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
|
||||
|
|
|
|||
|
|
@ -17,101 +17,13 @@
|
|||
*
|
||||
*/
|
||||
|
||||
module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
|
||||
module \$__SHREG_ (input C, input D, input E, output Q);
|
||||
parameter DEPTH = 0;
|
||||
parameter [DEPTH-1:0] INIT = 0;
|
||||
parameter CLKPOL = 1;
|
||||
parameter ENPOL = 2;
|
||||
wire CE;
|
||||
|
||||
// shregmap's INIT parameter shifts out LSB first;
|
||||
// however Xilinx expects MSB first
|
||||
function [DEPTH-1:0] brev;
|
||||
input [DEPTH-1:0] din;
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < DEPTH; i=i+1)
|
||||
brev[i] = din[DEPTH-1-i];
|
||||
end
|
||||
endfunction
|
||||
localparam [DEPTH-1:0] INIT_R = brev(INIT);
|
||||
|
||||
parameter _TECHMAP_CONSTMSK_L_ = 0;
|
||||
parameter _TECHMAP_CONSTVAL_L_ = 0;
|
||||
|
||||
generate
|
||||
if (ENPOL == 0)
|
||||
assign CE = ~E;
|
||||
else if (ENPOL == 1)
|
||||
assign CE = E;
|
||||
else
|
||||
assign CE = 1'b1;
|
||||
if (DEPTH == 1) begin
|
||||
wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0;
|
||||
if (CLKPOL)
|
||||
FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
else
|
||||
FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
end else
|
||||
if (DEPTH <= 16) begin
|
||||
SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 17 && DEPTH <= 32) begin
|
||||
SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 33 && DEPTH <= 64) begin
|
||||
wire T0, T1, T2;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
\$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T2;
|
||||
else
|
||||
MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
|
||||
end else
|
||||
if (DEPTH > 65 && DEPTH <= 96) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
\$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T4;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
|
||||
end
|
||||
end else
|
||||
if (DEPTH > 97 && DEPTH <= 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
\$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T6;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
|
||||
end
|
||||
end
|
||||
else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
|
||||
// Handle cases where depth is just 1 over a convenient value,
|
||||
if (&_TECHMAP_CONSTMSK_L_) begin
|
||||
// For constant length, use the flop
|
||||
wire T0;
|
||||
\$__SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0));
|
||||
\$__SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q));
|
||||
end
|
||||
else begin
|
||||
// For variable length, bump up to the next length
|
||||
\$__SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
|
||||
end
|
||||
end
|
||||
else begin
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
|
||||
end
|
||||
endgenerate
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));
|
||||
endmodule
|
||||
|
||||
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
|
||||
|
|
@ -135,22 +47,77 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
|
|||
parameter _TECHMAP_CONSTMSK_L_ = 0;
|
||||
parameter _TECHMAP_CONSTVAL_L_ = 0;
|
||||
|
||||
generate
|
||||
if (DEPTH == 1) begin
|
||||
\$__SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(0), .E(E), .Q(Q));
|
||||
end
|
||||
else if (DEPTH < 128) begin
|
||||
\$__SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
|
||||
end
|
||||
else if (DEPTH == 128) begin
|
||||
wire CE;
|
||||
generate
|
||||
if (ENPOL == 0)
|
||||
assign CE = ~E;
|
||||
else if (ENPOL == 1)
|
||||
assign CE = E;
|
||||
else
|
||||
assign CE = 1'b1;
|
||||
|
||||
if (DEPTH == 1) begin
|
||||
//wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0;
|
||||
if (CLKPOL)
|
||||
FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
else
|
||||
FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
|
||||
end else
|
||||
if (DEPTH <= 16) begin
|
||||
SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 17 && DEPTH <= 32) begin
|
||||
SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
|
||||
end else
|
||||
if (DEPTH > 33 && DEPTH <= 64) begin
|
||||
wire T0, T1, T2;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T2;
|
||||
else
|
||||
MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
|
||||
end else
|
||||
if (DEPTH > 65 && DEPTH <= 96) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T4;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
|
||||
end
|
||||
end else
|
||||
if (DEPTH > 97 && DEPTH < 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T6;
|
||||
else begin
|
||||
MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
|
||||
MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
|
||||
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
|
||||
end
|
||||
end
|
||||
else if (DEPTH < 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
|
||||
// Handle cases where depth is just 1 over a convenient value,
|
||||
if (&_TECHMAP_CONSTMSK_L_) begin
|
||||
// For constant length, use the flop
|
||||
wire T0;
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q));
|
||||
end
|
||||
else begin
|
||||
// For variable length, bump up to the next length
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
|
||||
end
|
||||
end
|
||||
else if (DEPTH == 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue