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MSVC does not understand __builtin_unreachable

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Anonymous Maarten 2020-06-17 13:52:45 +02:00
parent 35008e6d40
commit 504f220619
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/preproc.cc
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@ -591,7 +591,7 @@ read_define_args()
default: default:
// The only FSM states are 0-2 and we dealt with 2 at the start of the loop. // The only FSM states are 0-2 and we dealt with 2 at the start of the loop.
__builtin_unreachable(); log_assert(false);
} }
} }