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https://github.com/YosysHQ/yosys
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functional backend: add different types of input/output/state variables
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parent
79a1b691ea
commit
50047d25b3
5 changed files with 237 additions and 120 deletions
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@ -150,8 +150,8 @@ template<class NodePrinter> struct CxxPrintVisitor : public Functional::Abstract
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void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
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void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
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void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
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void input(Node, IdString name) override { print("input.{}", input_struct[name]); }
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void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
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void input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); print("input.{}", input_struct[name]); }
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void state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); print("current_state.{}", state_struct[name]); }
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void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
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void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); }
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};
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@ -175,12 +175,12 @@ struct CxxModule {
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output_struct("Outputs"),
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state_struct("State")
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{
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for (auto [name, sort] : ir.inputs())
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input_struct.insert(name, sort);
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for (auto [name, sort] : ir.outputs())
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output_struct.insert(name, sort);
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for (auto [name, sort] : ir.state())
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state_struct.insert(name, sort);
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for (auto input : ir.inputs())
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input_struct.insert(input->name, input->sort);
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for (auto output : ir.outputs())
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output_struct.insert(output->name, output->sort);
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for (auto state : ir.states())
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state_struct.insert(state->name, state->sort);
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module_name = CxxScope<int>().unique_name(module->name);
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}
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void write_header(CxxWriter &f) {
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@ -197,19 +197,19 @@ struct CxxModule {
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}
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void write_initial_def(CxxWriter &f) {
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f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name);
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for (auto [name, sort] : ir.state()) {
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if (sort.is_signal())
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f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name)));
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else if (sort.is_memory()) {
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for (auto state : ir.states()) {
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if (state->sort.is_signal())
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f.print("\tstate.{} = {};\n", state_struct[state->name], cxx_const(state->initial_value_signal()));
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else if (state->sort.is_memory()) {
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f.print("\t{{\n");
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f.print("\t\tstd::array<Signal<{}>, {}> mem;\n", sort.data_width(), 1<<sort.addr_width());
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const auto &contents = ir.get_initial_state_memory(name);
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f.print("\t\tstd::array<Signal<{}>, {}> mem;\n", state->sort.data_width(), 1<<state->sort.addr_width());
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const auto &contents = state->initial_value_memory();
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f.print("\t\tmem.fill({});\n", cxx_const(contents.default_value()));
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for(auto range : contents)
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for(auto addr = range.base(); addr < range.limit(); addr++)
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if(!equal_def(range[addr], contents.default_value()))
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f.print("\t\tmem[{}] = {};\n", addr, cxx_const(range[addr]));
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f.print("\t\tstate.{} = mem;\n", state_struct[name]);
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f.print("\t\tstate.{} = mem;\n", state_struct[state->name]);
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f.print("\t}}\n");
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}
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}
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@ -229,10 +229,10 @@ struct CxxModule {
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node.visit(printVisitor);
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f.print(";\n");
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}
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for (auto [name, sort] : ir.state())
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f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name)));
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for (auto [name, sort] : ir.outputs())
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f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name)));
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for (auto state : ir.states())
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f.print("\tnext_state.{} = {};\n", state_struct[state->name], node_name(state->next_value()));
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for (auto output : ir.outputs())
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f.print("\toutput.{} = {};\n", output_struct[output->name], node_name(output->value()));
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f.print("}}\n\n");
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}
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};
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