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cxxrtl: store comb $print cell last EN/ARGS in module

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statics were obviously wrong -- may be multiple instantiations of any
given module.  Extend test to cover this.
This commit is contained in:
Charlotte 2023-06-28 11:51:31 +10:00 committed by Marcelina Kościelnicka
parent 843ad9331b
commit 4ffdee65e0
3 changed files with 21 additions and 26 deletions
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35
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -1219,12 +1219,13 @@ struct CxxrtlWorker {
log_assert(!for_debug); log_assert(!for_debug);
auto trg_enable = cell->getParam(ID::TRG_ENABLE).as_bool(); auto trg_enable = cell->getParam(ID::TRG_ENABLE).as_bool();
static int cell_counter = 0;
if (!trg_enable) { if (!trg_enable) {
++cell_counter; f << indent << "auto " << mangle(cell) << "_curr = ";
f << indent << "static bool last_print_" << cell_counter << "_known = false;\n"; dump_sigspec_rhs(cell->getPort(ID::EN));
f << indent << "static value<1> last_print_" << cell_counter << "_en;\n"; f << ".concat(";
f << indent << "static value<" << cell->getPort(ID::ARGS).size() << "> last_print_" << cell_counter << "_args;\n"; dump_sigspec_rhs(cell->getPort(ID::ARGS));
f << ").val();\n";
} }
f << indent << "if ("; f << indent << "if (";
@ -1246,16 +1247,7 @@ struct CxxrtlWorker {
} }
f << ") && "; f << ") && ";
} else { } else {
f << '('; f << mangle(cell) << " != " << mangle(cell) << "_curr && ";
f << "!last_print_" << cell_counter << "_known || ";
f << '(';
f << "last_print_" << cell_counter << "_en != ";
dump_sigspec_rhs(cell->getPort(ID::EN));
f << " || last_print_" << cell_counter << "_args != ";
dump_sigspec_rhs(cell->getPort(ID::ARGS));
f << ')';
f << ") && ";
} }
dump_sigspec_rhs(cell->getPort(ID::EN)); dump_sigspec_rhs(cell->getPort(ID::EN));
f << " == value<1>{1u}) {\n"; f << " == value<1>{1u}) {\n";
@ -1265,13 +1257,7 @@ struct CxxrtlWorker {
f << indent << "}\n"; f << indent << "}\n";
if (!trg_enable) { if (!trg_enable) {
f << indent << "last_print_" << cell_counter << "_known = true;\n"; f << indent << mangle(cell) << " = " << mangle(cell) << "_curr;\n";
f << indent << "last_print_" << cell_counter << "_en = ";
dump_sigspec_rhs(cell->getPort(ID::EN));
f << ";\n";
f << indent << "last_print_" << cell_counter << "_args = ";
dump_sigspec_rhs(cell->getPort(ID::ARGS));
f << ";\n";
} }
// Flip-flops // Flip-flops
} else if (is_ff_cell(cell->type)) { } else if (is_ff_cell(cell->type)) {
@ -2362,6 +2348,11 @@ struct CxxrtlWorker {
f << "\n"; f << "\n";
bool has_cells = false; bool has_cells = false;
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool()) {
// comb $print cell -- store the last EN/ARGS values to know when they change.
dump_attrs(cell);
f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n";
}
if (is_internal_cell(cell->type)) if (is_internal_cell(cell->type))
continue; continue;
dump_attrs(cell); dump_attrs(cell);

9
tests/fmt/always_comb_tb.cc
View file

@ -3,11 +3,14 @@
int main() int main()
{ {
cxxrtl_design::p_top uut; cxxrtl_design::p_top uut1, uut2;
for (int i = 0; i < 20; ++i) { for (int i = 0; i < 20; ++i) {
uut.p_clk.set(!uut.p_clk); uut1.p_clk.set(!uut1.p_clk);
uut.step(); uut1.step();
uut2.p_clk.set(!uut2.p_clk);
uut2.step();
} }
return 0; return 0;

3
tests/fmt/always_comb_tb.v
View file

@ -1,7 +1,8 @@
module tb; module tb;
reg clk = 0; reg clk = 0;
top uut (.clk(clk)); top uut1 (.clk(clk));
top uut2 (.clk(clk));
always #1 clk <= ~clk; always #1 clk <= ~clk;
initial #20 $finish; initial #20 $finish;