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genrtlil: add width detection for AST_PREFIX nodes

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Zachary Snow 2021-07-29 12:35:22 -04:00 • committed by Zachary Snow
parent 87ef1dd805
commit 4fec3a85cd
2 changed files with 26 additions and 0 deletions
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18
tests/simple/loop_prefix_case.v Normal file
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@ -0,0 +1,18 @@
module top(
input wire x,
output reg y
);
localparam I = 1;
genvar i;
generate
for (i = 0; i < 1; i = i + 1) begin : blk
wire [i:i] z = x;
end
endgenerate
always @* begin
case (blk[I - 1].z)
1: y = 0;
0: y = 1;
endcase
end
endmodule