mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-19 04:13:39 +00:00
Code Activity

verilog: allow spaces in macro arguments

Browse source
This commit is contained in:
Zachary Snow 2021-01-20 08:49:32 -07:00
parent 4762cc06c6
commit 4fadcc8f25
2 changed files with 28 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verilog/preproc.cc
View file

@ -392,7 +392,6 @@ static bool read_argument(std::string &dest)
{
std::vector<char> openers;
for (;;) {
skip_spaces();
std::string tok = next_token(true);
if (tok == ")") {
if (openers.empty())