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Merge pull request #1724 from YosysHQ/eddie/abc9_specify

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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
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Eddie Hung 2020-03-02 12:32:27 -08:00 • committed by GitHub
commit 4f889b2f57
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43 changed files with 3439 additions and 1711 deletions
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18
tests/various/bug1480.ys
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@ -1,18 +0,0 @@
read_verilog << EOF
module top(...);
input signed [17:0] A;
input signed [17:0] B;
output X;
output Y;
wire [35:0] P;
assign P = A * B;
assign X = P[0];
assign Y = P[35];
endmodule
EOF
synth_xilinx

2
tests/various/pmux2shiftx.v
View file

@ -33,7 +33,7 @@ module pmux2shiftx_test (
end
endmodule
module issue01135(input [7:0] i, output o);
module issue01135(input [7:0] i, output reg o);
always @*
case (i[6:3])
4: o <= i[0];