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sv: allow typenames as function return types

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Zachary Snow 2021-03-18 13:38:25 -04:00 • committed by Zachary Snow
parent 6a0d1e117d
commit 4f4e70876f
3 changed files with 46 additions and 0 deletions
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6
frontends/verilog/verilog_parser.y
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@ -861,6 +861,7 @@ task_func_decl:
outreg->children.push_back($4);
outreg->is_signed = $4->is_signed;
$4->is_signed = false;
outreg->is_custom_type = $4->type == AST_WIRETYPE;
}
current_function_or_task->children.push_back(outreg);
current_function_or_task_port_id = 1;
@ -871,6 +872,11 @@ task_func_decl:
};
func_return_type:
hierarchical_type_id {
$$ = new AstNode(AST_WIRETYPE);
$$->str = *$1;
delete $1;
} |
opt_type_vec opt_signedness_default_unsigned {
$$ = makeRange(0, 0, $2);
} |