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Cleaned up CSA tests.

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nella 2026-03-27 16:14:07 +01:00 • committed by nella
parent 9cc2e7d95e
commit 4f4c820f73
14 changed files with 636 additions and 806 deletions
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27
tests/csa_tree/csa_tree_idempotent.ys
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@ -17,3 +17,30 @@ csa_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_idempotent(
input [15:0] a, b, c, d, e, f, g, h,
output [15:0] y
);
assign y = a + b + c + d + e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
select -assert-none t:$alu
csa_tree
select -assert-count 6 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$sub
select -assert-none t:$alu
design -reset