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Cleaned up CSA tests.

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nella 2026-03-27 16:14:07 +01:00 • committed by nella
parent 9cc2e7d95e
commit 4f4c820f73
14 changed files with 636 additions and 806 deletions
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36
tests/csa_tree/csa_tree_equiv.ys
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@ -96,6 +96,22 @@ select -assert-count 1 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module equiv_sub_3op(
input [3:0] a, b, c,
output [3:0] y
);
assign y = a - b + c;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt csa_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module equiv_sub_mixed(
input [3:0] a, b, c, d,
@ -108,7 +124,7 @@ hierarchy -auto-top
proc
equiv_opt csa_tree
design -load postopt
select -assert-count 3 t:$fa
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
@ -124,23 +140,7 @@ hierarchy -auto-top
proc
equiv_opt csa_tree
design -load postopt
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module equiv_sub_3op(
input [3:0] a, b, c,
output [3:0] y
);
assign y = a - b + c;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt csa_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset