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Cleaned up CSA tests.

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nella 2026-03-27 16:14:07 +01:00 • committed by nella
parent 9cc2e7d95e
commit 4f4c820f73
14 changed files with 636 additions and 806 deletions
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260
tests/csa_tree/csa_tree_edge_cases.ys
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@ -145,3 +145,263 @@ csa_tree
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module alu_add2(
input [7:0] a, b,
output [7:0] y
);
assign y = a + b;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
select -assert-none t:$fa
select -assert-none t:$add
select -assert-none t:$sub
select -assert-count 1 t:$alu
design -reset
read_verilog <<EOT
module alu_sub2(
input [7:0] a, b,
output [7:0] y
);
assign y = a - b;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
select -assert-none t:$fa
select -assert-none t:$add
select -assert-none t:$sub
select -assert-count 1 t:$alu
design -reset
read_verilog <<EOT
module alu_compare(
input [7:0] a, b,
output y
);
assign y = (a < b);
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
select -assert-none t:$fa
select -assert-none t:$add
select -assert-none t:$sub
select -assert-count 1 t:$alu
design -reset
read_verilog <<EOT
module macc_mul(
input [7:0] a, b, c,
output [15:0] y
);
assign y = a * b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$fa
select -assert-min 1 t:$macc t:$macc_v2 %u
design -reset
read_verilog <<EOT
module alu_fanout(
input [7:0] a, b, c,
output [7:0] mid, y
);
wire [7:0] ab = a + b;
assign mid = ab;
assign y = ab + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-none t:$fa
select -assert-count 2 t:$alu
design -reset
read_verilog <<EOT
module macc_2port(
input [7:0] a, b,
output [7:0] y
);
assign y = a + b;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$fa
design -reset
read_verilog <<EOT
module alu_mixed_width(
input [7:0] a,
input [3:0] b,
input [15:0] c,
input [7:0] d,
output [15:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_signed(
input signed [7:0] a, b, c, d,
output signed [9:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module fir_4tap_alu(
input clk,
input [15:0] x, c0, c1, c2, c3,
output reg [31:0] y
);
reg [15:0] x1, x2, x3;
always @(posedge clk) begin
x1 <= x;
x2 <= x1;
x3 <= x2;
end
wire [31:0] sum = x*c0 + x1*c1 + x2*c2 + x3*c3;
always @(posedge clk) y <= sum;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-min 1 t:$dff
design -reset
read_verilog <<EOT
module alu_mixed_sign(
input signed [7:0] a,
input [7:0] b,
input signed [7:0] c,
output signed [9:0] y
);
assign y = a + b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 1 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_wide32(
input [31:0] a, b, c, d,
output [31:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_single(
input [7:0] a,
output [7:0] y
);
assign y = a;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
select -assert-none t:$fa
select -assert-none t:$add
select -assert-none t:$sub
select -assert-none t:$alu
design -reset
read_verilog <<EOT
module macc_mul_survives(
input [7:0] a, b, c, d,
output [15:0] y
);
assign y = a * b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$fa
select -assert-min 1 t:$macc t:$macc_v2 %u
design -reset