mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-27 08:28:45 +00:00
Code Activity

write_json to not write contents (cells/wires) of whiteboxes

Browse source
This commit is contained in:
Eddie Hung 2019-04-18 10:30:45 -07:00
parent 290a798cec
commit 4ef03e19a8
1 changed files with 59 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

115
backends/json/json.cc
View file

@ -130,72 +130,75 @@ struct JsonWriter
f << stringf(" }"); f << stringf(" }");
first = false; first = false;
} }
f << stringf("\n },\n"); f << stringf("\n }");
f << stringf(" \"cells\": {"); if (!module->get_blackbox_attribute()) {
first = true; f << stringf(",\n \"cells\": {");
for (auto c : module->cells()) { first = true;
if (use_selection && !module->selected(c)) for (auto c : module->cells()) {
continue; if (use_selection && !module->selected(c))
f << stringf("%s\n", first ? "" : ","); continue;
f << stringf(" %s: {\n", get_name(c->name).c_str()); f << stringf("%s\n", first ? "" : ",");
f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0"); f << stringf(" %s: {\n", get_name(c->name).c_str());
f << stringf(" \"type\": %s,\n", get_name(c->type).c_str()); f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
if (aig_mode) { f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
Aig aig(c); if (aig_mode) {
if (!aig.name.empty()) { Aig aig(c);
f << stringf(" \"model\": \"%s\",\n", aig.name.c_str()); if (!aig.name.empty()) {
aig_models.insert(aig); f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
aig_models.insert(aig);
}
} }
} f << stringf(" \"parameters\": {");
f << stringf(" \"parameters\": {"); write_parameters(c->parameters);
write_parameters(c->parameters); f << stringf("\n },\n");
f << stringf("\n },\n"); f << stringf(" \"attributes\": {");
f << stringf(" \"attributes\": {"); write_parameters(c->attributes);
write_parameters(c->attributes); f << stringf("\n },\n");
f << stringf("\n },\n"); if (c->known()) {
if (c->known()) { f << stringf(" \"port_directions\": {");
f << stringf(" \"port_directions\": {"); bool first2 = true;
for (auto &conn : c->connections()) {
string direction = "output";
if (c->input(conn.first))
direction = c->output(conn.first) ? "inout" : "input";
f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
first2 = false;
}
f << stringf("\n },\n");
}
f << stringf(" \"connections\": {");
bool first2 = true; bool first2 = true;
for (auto &conn : c->connections()) { for (auto &conn : c->connections()) {
string direction = "output";
if (c->input(conn.first))
direction = c->output(conn.first) ? "inout" : "input";
f << stringf("%s\n", first2 ? "" : ","); f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str()); f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
first2 = false; first2 = false;
} }
f << stringf("\n },\n"); f << stringf("\n }\n");
f << stringf(" }");
first = false;
} }
f << stringf(" \"connections\": {"); f << stringf("\n },\n");
bool first2 = true;
for (auto &conn : c->connections()) {
f << stringf("%s\n", first2 ? "" : ",");
f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
first2 = false;
}
f << stringf("\n }\n");
f << stringf(" }");
first = false;
}
f << stringf("\n },\n");
f << stringf(" \"netnames\": {"); f << stringf(" \"netnames\": {");
first = true; first = true;
for (auto w : module->wires()) { for (auto w : module->wires()) {
if (use_selection && !module->selected(w)) if (use_selection && !module->selected(w))
continue; continue;
f << stringf("%s\n", first ? "" : ","); f << stringf("%s\n", first ? "" : ",");
f << stringf(" %s: {\n", get_name(w->name).c_str()); f << stringf(" %s: {\n", get_name(w->name).c_str());
f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0"); f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
f << stringf(" \"bits\": %s,\n", get_bits(w).c_str()); f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
f << stringf(" \"attributes\": {"); f << stringf(" \"attributes\": {");
write_parameters(w->attributes); write_parameters(w->attributes);
f << stringf("\n }\n"); f << stringf("\n }\n");
f << stringf(" }"); f << stringf(" }");
first = false; first = false;
}
f << stringf("\n }");
} }
f << stringf("\n }\n"); f << stringf("\n");
f << stringf(" }"); f << stringf(" }");
} }