sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

tests/verilog/task_attr.ys

@@ -15,7 +15,7 @@ EOT
 select -assert-none a:* a:src %d
 
 
-logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+logger -expect error "syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT" 1
 design -reset
 read_verilog <<EOT
 module top;