sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

tests/verilog/asgn_expr_not_proc_1.ys

@@ -0,0 +1,7 @@
+logger -expect error "Assignments within expressions are only permitted within procedures." 1
+read_verilog -sv <<EOF
+module top;
+integer x, y;
+assign x = y++;
+endmodule
+EOF