sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

tests/verilog/asgn_expr.ys

@@ -0,0 +1,3 @@
+read_verilog -sv asgn_expr.sv
+proc
+sat -verify -prove-asserts -show-all