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sv: support assignments within expressions

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- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.
This commit is contained in:
Zachary Snow 2023-09-05 22:19:28 -04:00
parent 83b1a57eed
commit 4edb1a1921
15 changed files with 231 additions and 24 deletions
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README.md
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@ -592,6 +592,8 @@ from SystemVerilog:
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
- Assignments within expressions are supported.
Building the documentation
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