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Updates to install and tests

Browse source 
Includes CAD suite info and details on the OSS CAD suite nightly build targets.
Instructions for building from source, largely based on the readme but with some minor modifications.
Tests are still WIP, but we replaced the old test suites with a brief comment on the github workflow tests.  Still needs more on the tests themselves and how to run them locally.
Also an extra todo on the index page.
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Krystine Sherwin 2023-12-11 12:44:05 +13:00
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docs/source/test_suites.rst
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Test suites
===========
.. note:: Potentially significantly out of date information
last updated circa 2015
.. todo:: more about the included test suite
.. todo:: update content from 2015
Automatic testing
-----------------
Continuously checking the correctness of Yosys and making sure that new features
do not break old ones is a high priority in Yosys. Two external test suites
have been built for Yosys: VlogHammer and yosys-bigsim. In addition to that,
yosys comes with approx 200 test cases used in ``make test``. A debug build of
Yosys also contains a lot of asserts and checks the integrity of the internal
state after each command.
The `Yosys Git repo`_ has automatic testing of builds and running of the
included test suite on the following platforms:
VlogHammer
----------
- Ubuntu 20.04 (Focal Fossa) |test-linux|
- macOS 11 (Big Sur) |test-macos|
VlogHammer is a Verilog regression test suite developed to test the different
subsystems in Yosys by comparing them to each other and to the output created by
some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
.. _Yosys Git repo: https://github.com/YosysHQ/yosys
Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology
mapping, simulation models, SAT models.
Thousands of auto-generated test cases containing code such as:
.. code-block:: verilog
assign y9 = $signed(((+$signed((^(6'd2 ** a2))))<$unsigned($unsigned(((+a3))))));
assign y10 = (-((+((+{2{(~^p13)}})))^~(!{{b5,b1,a0},(a1&p12),(a4+a3)})));
assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))}));
Some bugs in Yosys were found and fixed thanks to VlogHammer. Over 50 bugs in
the other tools used as external reference where found and reported so far.
yosys-bigsim
------------
yosys-bigsim is a collection of real-world open-source Verilog designs and test
benches. yosys-bigsim compares the testbench outputs of simulations of the original
Verilog code and synthesis results.
The following designs are included in yosys-bigsim (excerpt):
- ``openmsp430`` -- an MSP430 compatible 16 bit CPU
- ``aes_5cycle_2stage`` -- an AES encryption core
- ``softusb_navre`` -- an AVR compatible 8 bit CPU
- ``amber23`` -- an ARMv2 compatible 32 bit CPU
- ``lm32`` -- another 32 bit CPU from Lattice Semiconductor
- ``verilog-pong`` -- a hardware pong game with VGA output
- ``elliptic_curve_group`` -- ECG point-add and point-scalar-mul core
- ``reed_solomon_decoder`` -- a Reed-Solomon Error Correction Decoder
Code available at https://github.com/YosysHQ/yosys-bigsim
.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=master
.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=master