From 4eb2d06676e7980bb3add066073bd98794689625 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 17 Jan 2025 11:24:38 +1300
Subject: [PATCH] cutpoint: Add -blackbox option

Replace the contents of all blackboxes in the design with a formal cut point.
Includes test script.
---
 passes/sat/cutpoint.cc             | 30 +++++++++++++++++++++++++--
 tests/various/cutpoint_blackbox.ys | 33 ++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 2 deletions(-)
 create mode 100644 tests/various/cutpoint_blackbox.ys

diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index bca6a5ec6..0ca422bfa 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -37,10 +37,15 @@ struct CutpointPass : public Pass {
 		log("        set cupoint nets to undef (x). the default behavior is to create a\n");
 		log("        $anyseq cell and drive the cutpoint net from that\n");
 		log("\n");
+		log("    cutpoint -blackbox [options]\n");
+		log("\n");
+		log("Replace the contents of all blackboxes in the design with a formal cut point.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		 bool flag_undef = false;
+		bool flag_undef = false;
+		bool flag_blackbox = false;
 
 		log_header(design, "Executing CUTPOINT pass.\n");
 
@@ -51,12 +56,29 @@ struct CutpointPass : public Pass {
 				flag_undef = true;
 				continue;
 			}
+			if (args[argidx] == "-blackbox") {
+				flag_blackbox = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
-		for (auto module : design->selected_modules())
+		if (flag_blackbox) {
+			if (!design->full_selection())
+				log_cmd_error("This command only operates on fully selected designs!\n");
+			RTLIL::Selection module_boxes(false);
+			for (auto module : design->modules())
+				if (module->get_blackbox_attribute())
+					module_boxes.select(module);
+			design->selection_stack.push_back(module_boxes);
+		}
+
+		for (auto module : design->modules())
 		{
+			if (!design->selected_module(module))
+				continue;
+
 			if (design->selected_whole_module(module->name)) {
 				log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
 				module->new_connections(std::vector<RTLIL::SigSig>());
@@ -68,6 +90,10 @@ struct CutpointPass : public Pass {
 						output_wires.push_back(wire);
 				for (auto wire : output_wires)
 					module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
+				if (module->get_blackbox_attribute()) {
+					module->set_bool_attribute(ID::blackbox, false);
+					module->set_bool_attribute(ID::whitebox, false);
+				}
 				continue;
 			}
 
diff --git a/tests/various/cutpoint_blackbox.ys b/tests/various/cutpoint_blackbox.ys
new file mode 100644
index 000000000..78ee46db6
--- /dev/null
+++ b/tests/various/cutpoint_blackbox.ys
@@ -0,0 +1,33 @@
+read_verilog -specify << EOT
+module top(input a, b, output o);
+    wire c, d;
+    bb bb1 (.a (a), .b (b), .o (c));
+    wb wb1 (.a (a), .b (b), .o (d));
+    some_mod some_inst (.a (c), .b (d), .o (o));
+endmodule
+
+(* blackbox *)
+module bb(input a, b, output o);
+assign o = a | b;
+specify
+	(a => o) = 1;
+endspecify
+endmodule
+
+(* whitebox *)
+module wb(input a, b, output o);
+assign o = a ^ b;
+endmodule
+
+module some_mod(input a, b, output o);
+assign o = a & b;
+endmodule
+EOT
+
+select top
+
+select -assert-count 0 t:$anyseq
+select -assert-count 2 =t:?b
+cutpoint -blackbox =*
+select -assert-count 2 t:$anyseq
+select -assert-count 2 t:?b