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https://github.com/YosysHQ/yosys
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Update some abc9_arrival times, add abc9_required times
This commit is contained in:
Eddie Hung
parent
3e14ff1667
commit
4eaa45091c
3 changed files with 220 additions and 24 deletions
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@ -1112,15 +1112,33 @@ module RAM16X1D_1 (
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endmodule
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module RAM32X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
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(* abc9_required=453 *)
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE,
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input A0, A1, A2, A3, A4,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
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(* abc9_required=245 *)
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input A0,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
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(* abc9_required=208 *)
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input A1,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
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(* abc9_required=147 *)
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input A2,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
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(* abc9_required=68 *)
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input A3,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
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(* abc9_required=66 *)
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input A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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parameter INIT = 32'h0;
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@ -1135,15 +1153,33 @@ module RAM32X1D (
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endmodule
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module RAM32X1D_1 (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
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(* abc9_required=453 *)
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE,
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input A0, A1, A2, A3, A4,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
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(* abc9_required=245 *)
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input A0,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
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(* abc9_required=208 *)
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input A1,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
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(* abc9_required=147 *)
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input A2,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
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(* abc9_required=68 *)
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input A3,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
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(* abc9_required=66 *)
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input A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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parameter INIT = 32'h0;
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@ -1158,15 +1194,36 @@ module RAM32X1D_1 (
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endmodule
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module RAM64X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
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(* abc9_required=453 *)
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE,
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input A0, A1, A2, A3, A4, A5,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
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(* abc9_required=362 *)
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input A0,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
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(* abc9_required=245 *)
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input A1,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
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(* abc9_required=208 *)
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input A2,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
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(* abc9_required=147 *)
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input A3,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
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(* abc9_required=68 *)
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input A4,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
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(* abc9_required=66 *)
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input A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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@ -1181,15 +1238,36 @@ module RAM64X1D (
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endmodule
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module RAM64X1D_1 (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
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(* abc9_required=453 *)
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE,
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input A0, A1, A2, A3, A4, A5,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
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(* abc9_required=362 *)
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input A0,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
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(* abc9_required=245 *)
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input A1,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
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(* abc9_required=208 *)
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input A2,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
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(* abc9_required=147 *)
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input A3,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
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(* abc9_required=68 *)
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input A4,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
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(* abc9_required=66 *)
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input A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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@ -1204,15 +1282,23 @@ module RAM64X1D_1 (
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endmodule
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module RAM128X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
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// plus 208ps to cross MUXF7
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(* abc9_arrival=1359 *)
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output DPO, SPO,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
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(* abc9_required=453 *)
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE,
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input [6:0] A, DPRA
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
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(* abc9_required="616 362 245 208 147 68 66" *)
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input [6:0] A,
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input [6:0] DPRA
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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@ -1244,15 +1330,44 @@ endmodule
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// Multi port.
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module RAM32M (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
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(* abc9_arrival="1153 1188" *)
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output [1:0] DOA,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1153 *)
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output [1:0] DOA, DOB, DOC, DOD,
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input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
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input [1:0] DIA, DIB, DIC, DID,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
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(* abc9_arrival="1161 1187" *)
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output [1:0] DOB,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
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(* abc9_arrival="1158 1180" *)
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output [1:0] DOC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
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(* abc9_arrival="1163 1190" *)
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output [1:0] DOD,
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input [4:0] ADDRA, ADDRB, ADDRC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792-L802
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(* abc9_required="245 208 147 68 66" *)
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input [4:0] ADDRD,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
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(* abc9_required="453 384" *)
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input [1:0] DIA,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
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(* abc9_required="461 354" *)
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input [1:0] DIB,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
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(* abc9_required="457 375" *)
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input [1:0] DIC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
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(* abc9_required="310 334" *)
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input [1:0] DID,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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input WCLK,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
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(* abc9_required=654 *)
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input WE
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);
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parameter [63:0] INIT_A = 64'h0000000000000000;
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parameter [63:0] INIT_B = 64'h0000000000000000;
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@ -1347,15 +1462,40 @@ module RAM32M16 (
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endmodule
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module RAM64M (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
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(* abc9_arrival=1153 *)
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output DOA, DOB, DOC, DOD,
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input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
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input DIA, DIB, DIC, DID,
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output DOA,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc9_arrival=1161 *)
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output DOB,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
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(* abc9_arrival=1158 *)
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output DOC,
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
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(* abc9_arrival=1163 *)
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output DOD,
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input [5:0] ADDRA, ADDRB, ADDRC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
|
||||
(* abc9_required="362 245 208 147 68 66" *)
|
||||
input [5:0] ADDRD,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
|
||||
(* abc9_required=384 *)
|
||||
input DIA,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
|
||||
(* abc9_required=354 *)
|
||||
input DIB,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
|
||||
(* abc9_required=375 *)
|
||||
input DIC,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
|
||||
(* abc9_required=310 *)
|
||||
input DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
input WCLK,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
|
||||
(* abc9_required=654 *)
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue