mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 20:05:52 +00:00
Code Activity

SigSet<Cell*> to use stable compare class

Browse source
This commit is contained in:
Eddie Hung 2019-09-12 11:45:02 -07:00
parent 6044fff074
commit 4ea34aaacd
5 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/scc.cc
View file

@ -116,7 +116,7 @@ struct SccWorker
}
SigPool selectedSignals;
SigSet<RTLIL::Cell*> sigToNextCells;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sigToNextCells;
for (auto &it : module->wires_)
if (design->selected(module, it.second))