mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	simlib: blackbox $print cell
				
					
				
			It's possible to `generate` the appropriate always blocks per the triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
This commit is contained in:
		
							parent
							
								
									fc0acd0ad1
								
							
						
					
					
						commit
						4e94f62116
					
				
					 1 changed files with 17 additions and 0 deletions
				
			
		|  | @ -1799,6 +1799,23 @@ end | |||
| 
 | ||||
| endmodule | ||||
| 
 | ||||
| // --------------------------------------------------------
 | ||||
| 
 | ||||
| module \$print (EN, TRG, ARGS); | ||||
| 
 | ||||
| parameter FORMAT = ""; | ||||
| parameter ARGS_WIDTH = 0; | ||||
| parameter TRG_ENABLE = 1; | ||||
| 
 | ||||
| parameter TRG_WIDTH = 0; | ||||
| parameter TRG_POLARITY = 0; | ||||
| 
 | ||||
| input EN; | ||||
| input [TRG_WIDTH-1:0] TRG; | ||||
| input [ARGS_WIDTH-1:0] ARGS; | ||||
| 
 | ||||
| endmodule | ||||
| 
 | ||||
| // --------------------------------------------------------
 | ||||
| `ifndef SIMLIB_NOSR | ||||
| 
 | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue