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https://github.com/YosysHQ/yosys
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Merge pull request #97 from Silimate/reg-rename
Bug fix for reg_rename pass
This commit is contained in:
Akash Levy
GitHub
commit
4e937450b4
1 changed files with 166 additions and 116 deletions
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@ -18,15 +18,143 @@
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/fstdata.h"
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#include "kernel/yosys.h"
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#include <regex>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RegRenameInstance {
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std::string vcd_scope;
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Module *module;
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dict<Cell*, RegRenameInstance *> children;
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// Constructor
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// When constructing, it will recursively build the
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// module hierarchy with correct VCD scope mapping
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RegRenameInstance(std::string scope, Module *mod) : vcd_scope(scope), module(mod)
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{
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// Loop through all cells in the module
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for (auto cell : module->cells()) {
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Module *child = module->design->module(cell->type);
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if (child == nullptr) {
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continue; // skip non-module cells
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}
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// Construct the child's scope in VCD format,
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// which is the parent scope plus the instance name
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std::string child_scope = vcd_scope + "." + RTLIL::unescape_id(cell->name);
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children[cell] = new RegRenameInstance(child_scope, child);
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}
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}
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// Destructor
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~RegRenameInstance()
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{
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for (auto &it : children)
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delete it.second;
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}
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// Processes registers in a given module hierarchy
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// and renames to allow for correct register annotation
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void process_registers(dict<std::pair<std::string, std::string>, int> &vcd_reg_widths)
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{
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std::regex reg_regex("(.*)_reg(?:\\[(\\d+)\\])?$");
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pool<Wire *> wiresToRemove;
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// Loop through all cells in the module
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for (auto cell : module->cells()) {
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// Skip non-register cells
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if (!RTLIL::builtin_ff_cell_types().count(cell->type)) {
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continue;
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}
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// Extract the register name from the cell name
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std::smatch match;
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std::string name = cell->name.c_str();
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if (!std::regex_match(name, match, reg_regex)) {
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log_warning("Unable to extract register name from cell %s\n", name.c_str());
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continue;
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}
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// Register name
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std::string baseName = RTLIL::unescape_id(match[1].str());
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bool isMultiBit = match.size() > 2 && match[2].matched;
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for (auto conn : cell->connections()) {
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// Rename wires from the register output
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *oldWire = conn.second.as_wire();
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// Skip wires that are inputs or outputs
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if (oldWire->port_input || oldWire->port_output)
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continue;
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// If the register is multi-bit, we must create a new wire
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if (isMultiBit) {
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int index = std::stoi(match[2].str());
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// Lookup the original register width using the VCD scope
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// and netlist-extracted register name
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int origRegWidth = vcd_reg_widths[{vcd_scope, baseName}];
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if (origRegWidth == 0) { // if not found, log a warning and skip
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log_debug("Register '%s' with extracted name '%s' in scope '%s' not found in VCD\n",
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cell->name.c_str(), baseName.c_str(), vcd_scope.c_str());
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continue;
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}
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// Create a new wire for the multi-bit register if it doesn't exist already
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Wire *newWire = module->wire(RTLIL::escape_id(baseName));
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if (newWire == nullptr) {
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log_debug("Creating wire %s[%d:0] in scope %s\n", baseName.c_str(), origRegWidth - 1,
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vcd_scope.c_str());
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newWire = module->addWire(RTLIL::escape_id(baseName), origRegWidth);
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}
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// Log the connection of the new wire to the register
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log_debug("Connecting register wire %s[%d] to bit %d of %s in module %s\n",
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newWire->name.c_str(), index, index, log_id(newWire), log_id(module));
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// Replace old connection with a new one even at the input ports of subsequent cells from the register
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// output
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auto rewriter = [&](SigSpec &sig) { sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1)); };
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module->rewrite_sigspecs(rewriter);
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// Add the old wires to the list of wires to delete after processing
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wiresToRemove.insert(oldWire);
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} else {
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// Single-bit register rename
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IdString target_name = RTLIL::escape_id(baseName);
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if (oldWire->name != target_name && !module->wire(target_name)) {
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log_debug("Renaming %s to %s in scope %s\n", oldWire->name.c_str(), target_name.c_str(),
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vcd_scope.c_str());
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module->rename(oldWire, target_name);
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}
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}
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}
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}
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}
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// Delete the old unused wires
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module->remove(wiresToRemove);
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}
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void process_all(dict<std::pair<std::string, std::string>, int> &vcd_reg_widths)
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{
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process_registers(vcd_reg_widths);
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for (auto &it : children)
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it.second->process_all(vcd_reg_widths);
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}
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};
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struct RegRenamePass : public Pass {
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RegRenamePass() : Pass("reg_rename", "renames register output wires to the correct register name and creates new wires for multi-bit registers for correct VCD register annotations.") { }
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RegRenamePass()
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: Pass("reg_rename", "renames register output wires to the correct "
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"register name and creates new wires for multi-bit registers for "
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"correct VCD register annotations.")
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{
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -35,154 +163,76 @@ struct RegRenamePass : public Pass {
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log("\n");
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log(" -vcd <filename>\n");
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log(" vcd file to extract original register width from\n");
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log(" -scope <scope>\n");
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log(" scope to process in vcd file\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing reg_rename pass\n");
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// Argument parsing
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std::string vcd_filename;
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std::string scope;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
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if (args[argidx] == "-vcd" && argidx + 1 < args.size()) {
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vcd_filename = args[++argidx];
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continue;
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}
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if (args[argidx] == "-scope" && argidx + 1 < args.size()) {
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scope = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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// Populate data structure with register widths from VCD file
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dict<std::string, int> vcd_reg_widths;
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// Extract pre-optimization register widths from VCD file
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dict<std::pair<std::string, std::string>, int> vcd_reg_widths;
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if (!vcd_filename.empty()) {
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if (scope.empty()) {
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log_error("No scope provided. Use -scope option.\n");
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}
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log("Reading VCD file: %s\n", vcd_filename.c_str());
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try {
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FstData fst(vcd_filename);
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// Iterate through all variables in the VCD file
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for (auto &var : fst.getVars()) {
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// Only process register variables
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if (var.is_reg) {
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std::string reg_vcd_scope = var.scope;
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std::string reg_name = var.name;
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// Remove bracket notation if present
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// Remove bracket notation if present to preserve register name
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if (auto pos = reg_name.find('['); pos != std::string::npos)
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reg_name.erase(pos);
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// Add RTLIL backslash prefix if not present
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if (reg_name.empty() || reg_name[0] != '\\')
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reg_name = "\\" + reg_name;
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vcd_reg_widths[reg_name] = var.width;
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log("Found register '%s' with width %d\n", reg_name.c_str(), var.width);
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// Map the register's vcd scope and name to
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// its original width for later lookup.
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vcd_reg_widths[{reg_vcd_scope, reg_name}] = var.width;
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log_debug("Found register '%s' in scope '%s' with width %d\n",
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reg_name.c_str(), reg_vcd_scope.c_str(), var.width);
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}
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}
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log("Extracted %d register widths from VCD file\n", GetSize(vcd_reg_widths));
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log("Extracted %d register widths from VCD\n", GetSize(vcd_reg_widths));
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} catch (const std::exception &e) {
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log_error("Failed to read VCD file '%s': %s\n", vcd_filename.c_str(), e.what());
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log_error("Failed to read VCD file '%s': %s\n",
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vcd_filename.c_str(), e.what());
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}
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} else {
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log_error("No VCD file provided. Please provide a VCD file with the -vcd option.\n");
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log_error("No VCD file provided. Use -vcd option.\n");
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}
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// Regex to match registers to output wires
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// .*_reg[NUMBER] or .*_reg, can match NUMBER and part before _reg
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std::regex reg_regex("(.*)_reg(?:\\[(\\d+)\\])?$");
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uint32_t count = 0;
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for (auto module : design->selected_modules()) {
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pool<Wire *> wiresToRemove; // pool of wires to remove from the netlist
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for (auto cell : module->selected_cells()) {
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// STEP 2: Build hierarchy and process
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Module *topmod = design->top_module();
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if (!topmod)
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log_error("No top module found!\n");
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log("Building hierarchy from scope: %s\n", scope.c_str());
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// Only check register cell
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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// Build hierarchy and process register renamings
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RegRenameInstance *root = new RegRenameInstance(scope, topmod);
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root->process_all(vcd_reg_widths);
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delete root;
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// Rename register output wires to corresponding testbench names
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std::smatch match;
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std::string name = cell->name.c_str();
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if (std::regex_match(name, match, reg_regex)) {
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// baseName is the part before _reg
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std::string baseName = match[1].str();
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// Check if the register is a multi-bit register (look for [NUMBER] match in regex)
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bool isMultiBit = match.size() > 2 && match[2].matched;
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std::string indexStr;
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for (auto conn : cell->connections()) {
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if (conn.first == ID::Q && conn.second.is_wire()) {
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Wire *oldWire = conn.second.as_wire();
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// Skip if this wire is a module port (input/output)
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if (oldWire->port_input || oldWire->port_output) {
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log("Skipping port wire %s in register renaming for cell %s in module %s\n",
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oldWire->name.c_str(), log_id(cell), log_id(module));
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continue;
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}
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// Different cases for multi-bit and single-bit registers
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if (isMultiBit) {
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// Index of the register
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int index = 0;
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try {
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index = std::stoi(match[2].str());
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} catch (const std::exception &e) {
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log_warning("Failed to convert index %s to integer in register %s: %s\n",
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match[2].str().c_str(), log_id(cell), e.what());
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continue;
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}
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// Get or create the multi-bit wire
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Wire *newWire = module->wire(RTLIL::escape_id(baseName));
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if (newWire == nullptr) {
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// Wire doesn't exist, create it with the original register width
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int origRegWidth = vcd_reg_widths[baseName];
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if (origRegWidth == 0) {
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log_warning("Register '%s' not found in VCD file or has width 0\n", baseName.c_str());
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continue;
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}
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log("Creating multi-bit wire %s with width %d in module %s\n",
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baseName.c_str(), origRegWidth, log_id(module));
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newWire = module->addWire(RTLIL::escape_id(baseName), origRegWidth);
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}
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// Log that the new wire is being connected to the register
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log("Connecting register wire %s[%d] to bit %d of %s in module %s\n",
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newWire->name.c_str(), index, index, log_id(cell), log_id(module));
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// Replace all uses of oldWire with newWire[index]
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auto rewriter = [&](SigSpec &sig) {
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sig.replace(SigBit(oldWire), SigSpec(newWire, index, 1));
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};
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module->rewrite_sigspecs(rewriter);
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// Mark old wire for deletion
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log("Marking old wire %s for deletion in module %s\n",
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oldWire->name.c_str(), log_id(module));
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wiresToRemove.insert(oldWire);
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count++;
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} else {
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IdString target_name = RTLIL::escape_id(baseName);
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if (oldWire->name != target_name) {
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// Check if target name already exists
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if (module->wire(target_name)) {
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log("Skipping rename: wire %s already exists in module %s\n",
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target_name.c_str(), log_id(module));
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} else {
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// Rename single-bit register to correct name from RTL
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log("Renaming register wire %s to %s for cell %s in module %s\n",
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oldWire->name.c_str(), target_name.c_str(), log_id(cell), log_id(module));
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module->rename(oldWire, target_name);
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count++;
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}
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}
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}
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}
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}
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}
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}
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}
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module->remove(wiresToRemove);
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}
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// End
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log("Renamed %d registers in %d modules\n", count, design->selected_modules().size());
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log_flush();
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}
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} RegRenamePass;
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