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Fixed all users of SigSpec::chunks_rw() and removed it

This commit is contained in:
Clifford Wolf 2014-07-23 15:36:09 +02:00
parent 85db102e13
commit 4e802eb7f6
11 changed files with 80 additions and 91 deletions

View file

@ -70,11 +70,9 @@ struct BruteForceEquivChecker
log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
if (ignore_x_mod1) {
sig1.expand(), sig2.expand();
for (size_t i = 0; i < sig1.chunks().size(); i++)
if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
sig1.optimize(), sig2.optimize();
for (int i = 0; i < SIZE(sig1); i++)
if (sig1[i] == RTLIL::State::Sx)
sig2[i] = RTLIL::State::Sx;
}
if (sig1 != sig2) {
@ -297,9 +295,9 @@ struct VlogHammerReporter
sig.expand();
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
for (int i = 0; i < sig.size(); i++)
if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
for (int i = 0; i < SIZE(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());