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Replaced ezDefaultSAT with ezSatPtr
This commit is contained in:
Clifford Wolf
parent
f778a4081c
commit
4e6ca7760f
12 changed files with 186 additions and 139 deletions
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@ -73,7 +73,7 @@ struct FindReducedInputs
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SigMap &sigmap;
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drivers_t &drivers;
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ezDefaultSAT ez;
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ezSatPtr ez;
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std::set<RTLIL::Cell*> ez_cells;
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SatGen satgen;
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@ -81,7 +81,7 @@ struct FindReducedInputs
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std::vector<int> sat_pi_uniq_bitvec;
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FindReducedInputs(SigMap &sigmap, drivers_t &drivers) :
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sigmap(sigmap), drivers(drivers), satgen(&ez, &sigmap)
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sigmap(sigmap), drivers(drivers), satgen(ez.get(), &sigmap)
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{
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satgen.model_undef = true;
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}
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@ -104,30 +104,30 @@ struct FindReducedInputs
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satgen.setContext(&sigmap, "A");
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int sat_a = satgen.importSigSpec(bit).front();
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ez.assume(ez.NOT(satgen.importUndefSigSpec(bit).front()));
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ez->assume(ez->NOT(satgen.importUndefSigSpec(bit).front()));
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satgen.setContext(&sigmap, "B");
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int sat_b = satgen.importSigSpec(bit).front();
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ez.assume(ez.NOT(satgen.importUndefSigSpec(bit).front()));
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ez->assume(ez->NOT(satgen.importUndefSigSpec(bit).front()));
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int idx = sat_pi.size();
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size_t idx_bits = get_bits(idx);
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if (sat_pi_uniq_bitvec.size() != idx_bits) {
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sat_pi_uniq_bitvec.push_back(ez.frozen_literal(stringf("uniq_%d", int(idx_bits)-1)));
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sat_pi_uniq_bitvec.push_back(ez->frozen_literal(stringf("uniq_%d", int(idx_bits)-1)));
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for (auto &it : sat_pi)
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ez.assume(ez.OR(ez.NOT(it.second), ez.NOT(sat_pi_uniq_bitvec.back())));
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ez->assume(ez->OR(ez->NOT(it.second), ez->NOT(sat_pi_uniq_bitvec.back())));
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}
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log_assert(sat_pi_uniq_bitvec.size() == idx_bits);
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sat_pi[bit] = ez.frozen_literal(stringf("p, falsei_%s", log_signal(bit)));
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ez.assume(ez.IFF(ez.XOR(sat_a, sat_b), sat_pi[bit]));
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sat_pi[bit] = ez->frozen_literal(stringf("p, falsei_%s", log_signal(bit)));
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ez->assume(ez->IFF(ez->XOR(sat_a, sat_b), sat_pi[bit]));
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for (size_t i = 0; i < idx_bits; i++)
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if ((idx & (1 << i)) == 0)
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ez.assume(ez.OR(ez.NOT(sat_pi[bit]), ez.NOT(sat_pi_uniq_bitvec[i])));
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ez->assume(ez->OR(ez->NOT(sat_pi[bit]), ez->NOT(sat_pi_uniq_bitvec[i])));
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else
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ez.assume(ez.OR(ez.NOT(sat_pi[bit]), sat_pi_uniq_bitvec[i]));
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ez->assume(ez->OR(ez->NOT(sat_pi[bit]), sat_pi_uniq_bitvec[i]));
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}
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void register_cone_worker(std::set<RTLIL::SigBit> &pi, std::set<RTLIL::SigBit> &sigdone, RTLIL::SigBit out)
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@ -201,7 +201,7 @@ struct FindReducedInputs
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model_expr.push_back(sat_pi.at(pi[i]));
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}
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if (!ez.solve(model_expr, model, ez.expression(ezSAT::OpOr, model_expr), ez.XOR(output_a, output_b), ez.NOT(output_undef_a), ez.NOT(output_undef_b)))
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if (!ez->solve(model_expr, model, ez->expression(ezSAT::OpOr, model_expr), ez->XOR(output_a, output_b), ez->NOT(output_undef_a), ez->NOT(output_undef_b)))
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break;
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int found_count = 0;
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@ -230,7 +230,7 @@ struct PerformReduction
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drivers_t &drivers;
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std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs;
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ezDefaultSAT ez;
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ezSatPtr ez;
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SatGen satgen;
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std::vector<int> sat_pi, sat_out, sat_def;
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@ -260,7 +260,7 @@ struct PerformReduction
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} else {
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pi_bits.push_back(out);
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sat_pi.push_back(satgen.importSigSpec(out).front());
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ez.assume(ez.NOT(satgen.importUndefSigSpec(out).front()));
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ez->assume(ez->NOT(satgen.importUndefSigSpec(out).front()));
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sigdepth[out] = 0;
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}
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@ -268,7 +268,7 @@ struct PerformReduction
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}
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PerformReduction(SigMap &sigmap, drivers_t &drivers, std::set<std::pair<RTLIL::SigBit, RTLIL::SigBit>> &inv_pairs, std::vector<RTLIL::SigBit> &bits, int cone_size) :
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sigmap(sigmap), drivers(drivers), inv_pairs(inv_pairs), satgen(&ez, &sigmap), out_bits(bits), cone_size(cone_size)
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sigmap(sigmap), drivers(drivers), inv_pairs(inv_pairs), satgen(ez.get(), &sigmap), out_bits(bits), cone_size(cone_size)
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{
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satgen.model_undef = true;
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@ -278,15 +278,15 @@ struct PerformReduction
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for (auto &bit : bits) {
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out_depth.push_back(register_cone_worker(celldone, sigdepth, bit));
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sat_out.push_back(satgen.importSigSpec(bit).front());
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sat_def.push_back(ez.NOT(satgen.importUndefSigSpec(bit).front()));
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sat_def.push_back(ez->NOT(satgen.importUndefSigSpec(bit).front()));
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}
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if (inv_mode && cone_size > 0) {
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if (!ez.solve(sat_out, out_inverted, ez.expression(ezSAT::OpAnd, sat_def)))
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if (!ez->solve(sat_out, out_inverted, ez->expression(ezSAT::OpAnd, sat_def)))
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log_error("Solving for initial model failed!\n");
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for (size_t i = 0; i < sat_out.size(); i++)
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if (out_inverted.at(i))
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sat_out[i] = ez.NOT(sat_out[i]);
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sat_out[i] = ez->NOT(sat_out[i]);
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} else
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out_inverted = std::vector<bool>(sat_out.size(), false);
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}
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@ -296,8 +296,8 @@ struct PerformReduction
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if (verbose_level == 1)
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log(" Finding const value for %s.\n", log_signal(out_bits[idx]));
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bool can_be_set = ez.solve(ez.AND(sat_out[idx], sat_def[idx]));
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bool can_be_clr = ez.solve(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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bool can_be_set = ez->solve(ez->AND(sat_out[idx], sat_def[idx]));
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bool can_be_clr = ez->solve(ez->AND(ez->NOT(sat_out[idx]), sat_def[idx]));
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log_assert(!can_be_set || !can_be_clr);
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RTLIL::SigBit value(RTLIL::State::Sx);
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@ -355,8 +355,8 @@ struct PerformReduction
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std::vector<int> sat_set_list, sat_clr_list;
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for (int idx : bucket) {
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sat_set_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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sat_set_list.push_back(ez->AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez->AND(ez->NOT(sat_out[idx]), sat_def[idx]));
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}
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std::vector<int> modelVars = sat_out;
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@ -366,7 +366,7 @@ struct PerformReduction
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if (verbose_level >= 2)
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modelVars.insert(modelVars.end(), sat_pi.begin(), sat_pi.end());
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_set_list), ez.expression(ezSAT::OpOr, sat_clr_list)))
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if (ez->solve(modelVars, model, ez->expression(ezSAT::OpOr, sat_set_list), ez->expression(ezSAT::OpOr, sat_clr_list)))
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{
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int iter_count = 1;
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@ -379,13 +379,13 @@ struct PerformReduction
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for (int idx : bucket)
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if (!model[sat_out.size() + idx]) {
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sat_set_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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sat_set_list.push_back(ez->AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez->AND(ez->NOT(sat_out[idx]), sat_def[idx]));
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} else {
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sat_def_list.push_back(sat_def[idx]);
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}
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if (!ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_set_list), ez.expression(ezSAT::OpOr, sat_clr_list), ez.expression(ezSAT::OpAnd, sat_def_list)))
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if (!ez->solve(modelVars, model, ez->expression(ezSAT::OpOr, sat_set_list), ez->expression(ezSAT::OpOr, sat_clr_list), ez->expression(ezSAT::OpAnd, sat_def_list)))
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break;
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iter_count++;
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}
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@ -431,7 +431,7 @@ struct PerformReduction
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for (int idx2 : bucket)
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if (idx != idx2)
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sat_def_list.push_back(sat_def[idx2]);
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if (ez.solve(ez.NOT(sat_def[idx]), ez.expression(ezSAT::OpOr, sat_def_list)))
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if (ez->solve(ez->NOT(sat_def[idx]), ez->expression(ezSAT::OpOr, sat_def_list)))
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undef_slaves.push_back(idx);
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}
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@ -505,7 +505,7 @@ struct PerformReduction
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for (int idx2 : r)
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if (idx != idx2)
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sat_def_list.push_back(sat_def[idx2]);
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if (ez.solve(ez.NOT(sat_def[idx]), ez.expression(ezSAT::OpOr, sat_def_list)))
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if (ez->solve(ez->NOT(sat_def[idx]), ez->expression(ezSAT::OpOr, sat_def_list)))
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undef_slaves.push_back(idx);
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}
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